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Table 15-76. General Configuration Sequence for UART mode
Register
CR
CSR
SICR
0x00000000
0x08000000
MR1
MR2
CTUR
CTLR
RFALARM
TFALARM
IMR
Port_Config
0x00000005
CR
15.3.2
PSC in Codec Mode
After reset all PSCs are in UART mode. PSC1,2,3 and 6 can be put to one of the Codec modes by writing the appropriate value to the
register. The other values should be initialized at the same time. During Codec mode the PSC can connect to Codec interfaces with 8, 16, 24
or 32 bit data. For all these modes the PSC can be programmed to behave as a "normal soft modem" interface, SPI, ESAI or I2S interface.
The PSC Codec supports for all these modes the master mode (PSC drive the BitClk and FrameSync signal) or slave mode (PSC receive the
BitClk and FrameSync signals) functionality. Independently from the mode (master or slave) the PSC can provide an Mclk (master clock) for
an external Codec device. This behavior eliminates the need for an external crystal for the external Codec device.
simplified block Diagram for the PSC Codec mode. The
Codec mode.
Table 15-77
shows the signal assignment for all PSC Code modes.
Mode
"normal" Codec
ESAI
I2S
SPI Master
SPI Slave
The important register to configure the PSC for Codec mode are:
•
SICR
register - select the Codec mode
•
for master mode:
— cdm_pscX_bitclk_config - select Mclk frequency, see
— cdm_clock_enable_register- enable Mclk, see
— CCR- select BitClk and FrameSync Frequency
—
CTUR
- select FrameSync width
•
RFALARM,
TFALARM
•
CR
register - enable or disable receiver and transmitter
•
Port_config - select the right Pin-Muxing,
Freescale Semiconductor
Value
0x0A
Disable the Tx and Rx part for configuration if the PSC was enabled by the work
before.
0xdd00
select the clock source
Select the UART mode
or
0xXX
Select Error Mode, Parity Mode and the Parity Type
0xXX
Select Channel Mode, Port Control and Stop-Bit Length
0x00
set the Baud rate to 9600 with IPB clock frequency 66 MHz
0xD7
0x0XXX
Choose Rx FIFO "almost full" threshold level.
0x0XXX
Choose Tx FIFO "almost empty" threshold level.
0xXXXX
select the desired interrupt
Select the Pin-Muxing for UART mode for PSC1, see
Descriptions
0x05
Enable Tx and Rx
Chapter 2, Signal Descriptions
Table 15-77. Signal Definition for all Codec Modes
TXD
SDATA_out
MOSI
MISO
Section 5.5.6, CDM Clock Enable Register—MBAR + 0x0214
- select the FIFO "Alarm" level
Chapter 2, Signal Descriptions
MPC5200B Users Guide, Rev. 1
Setting
shows only the PSC signal names for the "normal"
Signal name
RXD
CLK
SDATA_in
SCK
MISO
SCK
MOSI
SCK
Section 5.5.11, PSC1 Mclock Config Register—MBAR + 0x0228
PSC Operation Modes
Chapter 2, Signal
SICR
Figure 15-6
shows a
FrameSync
LRCK
SS
SS
15-49
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