Freescale Semiconductor MPC5200B User Manual page 318

8:11 Reserved
12:15 Window 1Control
[3:0]
16:19 Reserved
20:23 Window 0 Control
[3:0]
24:31 Reserved
10.3.2.9 Initiator Control Register PCIICR(RW) —MBAR + 0x0D84
msb 1
0
R Reserved
W
RESET 0 0
16 17
R
W
RESET 0 0
Bits Name
0:4 Reserved
5 Retry Error
Enable
(RE)
6 Initiator Abort
Enable
(IAE)
7 Target Abort
Enable
(TAE)
8:23 Reserved
24:31 Maximum
Retries
Freescale Semiconductor
Reserved register. Write a zero to this register.
Bit[3] - IO/M#.
Bit[2:1] - PRC.
Bit[0] - Enable.
Reserved register. Write a zero to this register.
Bit[3] - IO/M#.
Bit[2:1] - PRC.
Bit[0] - Enable.
Reserved register. Write a zero to this register.
2 3 4 5 6
REE IAE
0 0 0 0 0
18 19 20 21 22
Reserved
0 0 0 0 0
Unused bits. Software should write zero to this register.
This bit enables CPU Interrupt generation in the case of Retry Error termination of a packet
transmission. It may be desirable to mask CPU interrupts, but in such a case, software
should poll the status bits to prevent a possible lock-up condition.
This bit enables CPU Interrupt generation in the case of Initiator Abort termination of a
packet transmission. It may be desirable to mask CPU interrupts, but in such a case,
software should poll the status bits to prevent a possible lock-up condition.
This bit enables CPU Interrupt generation in the case of Target Abort termination of a packet
transmission. It may be desirable to mask CPU interrupts, but in such a case, software
should poll the status bits to prevent a possible lock-up condition.
Unused bits. Software should write zero to this register.
This bit field controls the maximum number of automatic PCI retries to permit per
transaction. The retry counter is reset at the beginning of each transaction (i.e. it is not
cumulative). Setting the Maximum Retries to 0x00 allows infinite automatic retry cycles.
A finite (0x01 to 0xff) Maximum Retries value will detect the maximum PCI retries and the
next retry will abort the transaction. For a Write transaction an interrupt will be generated,
for a Read transaction an interrupt and a TEA on the XL Bus will be generated.
MPC5200B Users Guide, Rev. 1
7 8 9 10 11
TAE Reserved
0 0 0 0
23 24 25 26 27
Maximum Retries
0 1 1 1
Description
Registers
12 13 14 15
0 0 0 0 0
28 29 30 31 lsb
1 1 1 1 1
10-21