Table of Contents
Advertisement
Set TEOD bit in
DLCBCR2
For interrupt driven systems,
this marks the beginning of the
transmit Type 3 IFR section of
the BDLC module interrupt
service routine
Abandon IFR
transmit attempt
B
Jump to IFR
Receive Routine
NOTE: The EOF and CRC Error interrupts
are handled in the IFR Receive Routine
20.8.7
Receiving An In-Frame Response (IFR)
Receiving an In-Frame Response with the BDLC module is very similar to receiving a message frame. As each byte of an IFR is received,
the BDLC State Vector Register will indicate this to the CPU. An EOF indication in the BDLC State Vector Register indicates that the IFR
(and message) is complete. Also, the IMSG bit can also be used to command the BDLC module to mask any further network activity from
the CPU, including IFR bytes being received, until the next valid SOF is received.
Freescale Semiconductor
Enter Type 3 IFR
Transmit Routine
Write first IFR
byte to be transmitted
into DLCBDR
Set desired
TMIFR bit in DLCBCR2
Yes
Only one byte to
transmit?
No
Yes
Is DLCBSVR = $00?
No
Yes
Is DLCBSVR = $1C?
(Invalid Symbol)
No
Yes
Is DLCBSVR = $14?
(LOA)
No
No
Is DLCBSVR = $10?
(TDRE)
Yes
A
Figure 20-17. Transmitting A Type 3 IFR
MPC5200B Users Guide, Rev. 1
Functional Description
A
Load next byte to be
transmitted into DLCBDR
(clears TDRE)
No
Is this the last
byte?
Yes
Set TEOD bit
in DLCBCR2
Once BDLC module detects
EOF, IFR transmit
attempt is complete
Exit Type 3 IFR
Transmit Routine
B
20-43
Advertisement
Table of Contents
