Ictl Main Interrupt Status All Register—Mbar + 0X052C - Freescale Semiconductor MPC5200B User Manual

Interrupt Controller
Bits Name
0:3 —
— CSa[x]
4 CSa0
5 CSa1
6 CSa2
7 CSa3
8:31 —
Note:
1. No direct mask register is defined for critical interrupts. However, IRQ[0] can be masked by the MEE bit in Reg4, in which
case CSa status does not occur. If only the EENA[0] bit in
Register
is cleared, then CSa status occurs, but controller does not assert a e300 core interrupt.
7.2.4.11 ICTL Main Interrupt Status All Register—MBAR + 0x052C
msb 0 1
R
W
RESET: 0 0
16 17
R
W
RESET: 0 0
Bits Name
0:14 — Reserved
— MSa[x] Main Interrupt Status All. Indicates all pending interrupts. Is binary, showing each active
interrupt in its corresponding bit position. See Note 1.
Number in parenthesis indicates equivalent encoded value in MSe, Reg9.
15 MSa0 Slice_Timer 1 (SMI interrupt only)
16 MSa1 IRQ[1] input pin
17 MSa2 IRQ[2] input pin
18 MSa3 IRQ[3] input pin
19 MSa4 LO_int (some Peripheral source)
20 MSa5 RTC_periodic interrupt
21 MSa6 RTC_stopwatch interrupt
22 MSa7
GPIO std interrupt
7-16
Reserved
Critical Interrupt Status All—Indicates all pending interrupts, including the currently active
interrupt (if any). CSa is binary, showing each active interrupt input in its corresponding bit
position. See Note 1.
Number in parenthesis indicates equivalent encoded value in CSe, ICTL PerStat, MainStat,
CritStat Encoded Register.
indicates IRQ[0] interrupt
Slice Timer 0 interrupt
HI_int interrupt
WakeUp from deep-sleep mode (CCS) interrupt
Reserved
Table 7-14. ICTL Main Interrupt Status All Register
2 3 4 5 6
0 0 0 0 0
18 19 20 21 22
0 0 0 0 0
MPC5200B Users Guide, Rev. 1
Description
ICTL External Enable and External Types
7 8 9 10
Reserved
0 0 0 0
23 24 25 26
MSa
0 0 0 0
Description
11 12 13 14 15
MSa
0 0 0 0
27 28 29 30 31 lsb
0 0 0 0
Freescale Semiconductor
0
0