Table of Contents
Advertisement
Host Control (HC) Operational Registers
12.4.2
Control and Status Partition—MBAR + 0x1000
This HC partition uses 6 32-bit registers. These registers are located at an offset from MBAR of 0x1000. Register addresses are relative to
this offset. Therefore, the actual register address is:
The following registers are available:
•
USB HC Revision Register
•
USB HC Control Register
•
USB HC Command Status Register
•
USB HC Interrupt Status Register
•
USB HC Interrupt Enable Register
•
USB HC Interrupt Disable Register
12.4.2.1
USB HC Revision Register—MBAR + 0x1000
msb 0
1
R
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Bits
Name
0:23
–
24:31
REV
12.4.2.2
USB HC Control Register—MBAR + 0x1004
The HC Control register defines HC operating modes. Except for HostController FunctionalState and RemoteWakeUpConnected, most
fields in this register are modified only by the HCD.
msb 0
1
R
W
RESET:
0
0
16
17
R
Reserved
W
RESET:
0
0
12-6
MBAR + 0x1000 + register address
(0x1000)
(0x1004)
(0x1008)
(0x100C)
(0x1010)
(0x1014)
Table 12-1. USB HC Revision Register
2
3
4
5
6
0
0
0
0
0
18
19
20
21
22
Reserved
0
0
0
0
0
Reserved
Revision—a read-only field containing the BCD representation of the HCI specification
version implemented by this HC. For example, a value of 11h corresponds to version 1.1. All
HC implementations compliant with this specification have a value of 10h.
Table 12-2. USB HC Control Register
2
3
4
5
6
0
0
0
0
0
18
19
20
21
22
RWE RWC
0
0
0
0
0
MPC5200B Users Guide, Rev. 1
7
8
9
10
11
Reserved
0
0
0
0
23
24
25
26
27
0
0
0
0
Description
7
8
9
10
Reserved
0
0
0
0
23
24
25
26
IR
HCFS
BLE
CLE
0
0
0
0
12
13
14
15
0
0
0
0
0
28
29
30
31 lsb
REV
1
0
0
0
0
11
12
13
14
15
0
0
0
0
27
28
29
30
31 lsb
IE
PLE
CBSR
0
0
0
0
Freescale Semiconductor
0
0
Advertisement
Table of Contents
