Freescale Semiconductor MPC5200B User Manual page 533

PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00
Bit Name
8 DEOF
9 Error
10:11 —
12
CMD_SEND
13
DATA_OVR
14
DATA_VALID
15
UNEX_RX_
SLOT
15.2.12 Counter Timer Upper Register (0x18)
This write-only register holds the upper bytes of the preload value used by the timer to provide a given Baud rate. Reading from this register
shows the current value of the Baud rate generation counter.For a detailed description see the next section,
Lower Register (0x1C)—CTLR.
Table 15-30. Counter Timer Upper Register (0x18) for all Modes
msb 0
R
W
RESET: 0
Bit Name
0:7 CTUR
15-22
MIR / FIR Detect End of Frame
0 = DEOF has no effect on the interrupt.
1 = Enable the interrupt for DEOF.
other Modes—Reserved
Error
0 = Error bit in the ISR register has no effect on the interrupt.
1 = Enable the interrupt for Error
Reserved
Enhanced AC97 Mode—Command Send ready
0 = CMD_SEND bit in the
1 = Enable the interrupt for CMD_SEND
other Modes—Reserved
Enhanced AC97 Mode—Receive Data Overwrite
0 = DATA_OVR bit in the
1 = Enable the interrupt for DATA_OVR
other Modes—Reserved
Enhanced AC97 Mode—Received Status Data
0 = DATA_VALID bit in the
1 = Enable the interrupt for DATA_VALID
other Modes—Reserved
Enhanced AC97 Mode—Unexpected RX Slots detect
0 = UNEX_RX_SLOT bit in the
1 = Enable the interrupt for UNEX_RX_SLOT
other Modes—Reserved
1 2
0 0
Code—Frame Sync width, define the number of Bit clocks during the FrameSync signal is
active.
FrameSync Width = CTUR[0:7]+1
UART/ SIR/ SPI —Baud rate prescaler value.
Section 15.2.13, Counter Timer Lower Register (0x1C)—CTLR
See next section,
Other—Reserved
MPC5200B Users Guide, Rev. 1
Description
ISR register has no effect on the interrupt.
ISR register has no effect on the interrupt.
ISR register has no effect on the interrupt.
ISR register has no effect on the interrupt.
CTUR
—
3 4 5
Reserved
CTUR[0:7]
0 0 0
Description
Section 15.2.13, Counter Timer
6 7 lsb
0 0
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