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Bit
Name
0:6
—
7
ME
8:31
—
7.3.2.2.9
GPW WakeUp GPIO Data Input Values Register —MBAR + 0x0C20
msb 0
1
R
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Bit
Name
0:7
WIVAL
8:31
—
Freescale Semiconductor
Reserved
WakeUp GPIO Master Enable pin. This pin must be high before any WakeUp GPIO pin can
generate an interrupt. This bit should remain clear while programming individual interrupts
and then set high as a final step. This prevents any spurious interrupt occuring during
programming.
Reserved
Table 7-45. GPW WakeUp GPIO Data Input Values Register
2
3
4
5
6
WIVAL
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
Input Value bits for GPIO WakeUp pins 7–0. This is the raw state of the input pin at the time
this register is read. It is not latched to the state that caused the interrupt (if any).
This status bit is always available, regardless of any enable or setting. For example, even
if the pin is not used as GPIO.
Writing to this byte has no effect.
Bit 0 reflects GPIO_WKUP_7 (GPIO_WKUP_7 pin)
Bit 1 reflects GPIO_WKUP_6 (GPIO_WKUP_6 pin)
Bit 2 reflects GPIO_WKUP_5 (PSC6_1 pin)
Bit 3 reflects GPIO_WKUP_4 (PSC6_0 pin)
Bit 4 reflects GPIO_WKUP_3 (ETH_17 pin)
Bit 5 reflects GPIO_WKUP_2 (PSC3_9 pin)
Bit 6 reflects GPIO_WKUP_1 (PSC2_4 pin)
Bit 7 reflects GPIO_WKUP_0 (PSC1_4 pin)
Reserved
MPC5200B Users Guide, Rev. 1
Description
7
8
9
10
11
0
0
0
0
23
24
25
26
27
Reserved
0
0
0
0
Description
General Purpose I/O (GPIO)
12
13
14
15
Reserved
0
0
0
0
0
28
29
30
31 lsb
0
0
0
0
0
7-53
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