Fec Rx Fifo Data Register—Mbar + 0X3184; Fec Tx Fifo Data Register—Mbar + 0X31A4; Fec Rx Fifo Status Register—Mbar + 0X3188; Fec Tx Fifo Status Register—Mbar + 0X31A8 - Freescale Semiconductor MPC5200B User Manual

Freescale semiconductor board users guide
Table of Contents

Advertisement

FEC Tx FIFO Data Register—MBAR + 0x31A4
Address
0x1B4
0x1B8
0x1BC
0x1C0
14.6.1
FEC Rx FIFO Data Register—MBAR + 0x3184
14.7
FEC Tx FIFO Data Register—MBAR + 0x31A4
The RFIFO_DATA and TFIFO_DATA registers are the main interface port for the transmit and receive FIFO. Data which is to be buffered in
the FIFO, or has been buffered in the FIFO, is accessed through this register.
14.7.1
FEC Rx FIFO Status Register—MBAR + 0x3188
14.8
FEC Tx FIFO Status Register—MBAR + 0x31A8
The RFIFO_STATUS and TFIFO_STATUS registers contain bits which provide information about the status of the FIFO controller. The bits
marked sticky are cleared by writing a "1" to their positions.
msb 0
1
R
IP
TXW
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Bits
Name
0:3
4:7
Frame[0:3]
8
---
9
Error
14-28
Table 14-30. FIFO Interface Register Map (continued)
byte0
byte1
byte2
LWF
Alarm
Read
Write
Table 14-31. FEC Rx FIFO Status Register
FEC Tx FIFO Status Register
2
3
4
5
6
TYP
TYP
Frame[0:3]
E
E
[1]
[0[
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
Reserved
Frame Indicator – READ ONLY
This bus provides a frame status indicator for non-DMA applications.
Frame[0] = A frame boundary has occurred on the [31:24] byte of the data bus.
Frame[1] = A frame boundary has occurred on the [23:16] byte of the data bus.
Frame[2] = A frame boundary has occurred on the [15:8] byte of the data bus.
Frame[3] = A frame boundary has occurred on the [7:0] byte of the data bus.
Reserved
FIFO Error – Sticky, Write To Clear.
This bit signifies that an error has occurred in the FIFO controller. Errors can be caused by
underflow, overflow,or pointers being out of bounds. This bit will remain set until this bit of the
FIFO status register has been written with a 1.
MPC5200B Users Guide, Rev. 1
byte3
LWF
Transmit Last Write Frame Pointer
Alarm
Transmit (High/Low) Alarm Pointer
Read
Transmit FIFO Read Pointer
Write
Transmit FIFO Write Pointer
7
8
9
10
11
FAE
RXW
UF
OF
0
0
0
0
23
24
25
26
27
Reserved
0
0
0
0
Description
Description
12
13
14
15
FR
Full
Alarm
Empty
0
0
0
1
1
28
29
30
31 lsb
0
0
0
1
1
Freescale Semiconductor

Advertisement

Table of Contents
loading

Table of Contents