Freescale Semiconductor MPC5200B User Manual page 257

Memory Controller Registers (MBAR+0x0100:0x010C)
Device Structure
64Mbit 2Mx32bit
4M×16bit
8M×8bit
128Mbit 4M×32bit
8M×16bit
16M×8bit
256Mbit 8M×32bit
16M×16bit
32M×8bit
512Mbit 16M×32bit
32M×16bit
64M×8bit
1Gbit 32Mx32bit
64Mx16bit
2Gbit 64Mx32bit
a
All MEM_MA pins are driven in all cases, but only the bits used by memory are listed.
8-24
Table 8-8. 32-Bit SDRAM Address Multiplexing
Row bits ×
Col bits ×
hi_
Bank bits addr 4
a
11x8x2 0 —
12×8×2 0 —
12×9×2 0 —
13×8×2 1 —
12×8×2 0 —
12×9×2 0 —
13×8×2 1 —
12×10×2 0 —
13×9×2 1 —
12×9×2 0 —
13×8×2 1 —
12×10×2 0 —
13×9×2 1 —
12×11×2 0 — CA11
13×10×2 1 —
12×10×2 0 —
13×9×2 1 —
12×11×2 0 — CA11
13×10×2 1 —
12×12×2 0 CA12 CA11
13×11×2 1 CA11
12×11×2 0 — CA11
13×10×2 1 —
12×12×2 0 CA12 CA11
13×11×2 1 CA11
12×12×2 0 CA12 CA11
13×11×2 1 CA11
MPC5200B Users Guide, Rev. 1
Internal XLA[4:29]
5 6 7 8
— — — —
— — — RA[11:0]
— — CA8
— — RA12
— — — RA[11:0]
— — CA8
— — RA12
— CA9 CA8
— CA8 RA12
— — CA8 RA[11:0]
— — RA12
— CA9 CA8
— CA8 RA12
CA9 CA8
CA9 CA8 RA12
— CA9 CA8 RA[11:0]
— CA8 RA12
CA9 CA8
CA9 CA8 RA12
CA9 CA8
CA9 CA8 RA12
CA9 CA8 RA[11:0]
CA9 CA8 RA12
CA9 CA8
CA9 CA8 RA12
CA9 CA8 RA[11:0]
CA9 CA8 RA12
9:19 20:21 22:29
RA BA CA
[10:0] [1:0] [7:0]
BA CA
[1:0] [7:0]
BA CA
[1:0] [7:0]
BA CA
[1:0] [7:0]
BA CA
[1:0] [7:0]
BA CA
[1:0] [7:0]
Freescale Semiconductor