Functional Description ..........................................................................................................................................10-41

10.4.1

PCI Bus Protocol .............................................................................................................................................10-41

10.4.1.1

10.4.1.2

10.4.1.3

10.4.1.4

10.4.1.5

10.4.1.5.1

10.4.1.5.2

10.4.1.5.3

10.4.1.5.4

10.4.2

Initiator Arbitration .........................................................................................................................................10-48

10.4.2.1

10.4.3

Configuration Interface ...................................................................................................................................10-48

10.4.4

XL bus Initiator Interface ................................................................................................................................10-48

10.4.4.1

10.4.4.2

10.4.4.2.1

10.4.4.2.2

10.4.4.2.3

10.4.4.2.4

10.4.4.3

10.4.5

XL bus Target Interface .................................................................................................................................10-54

10.4.5.1

10.4.5.2

10.4.5.3

10.4.5.4

10.4.5.5

10.4.6

Communication Sub-System Initiator Interface .............................................................................................10-56

10.4.6.1

Freescale Semiconductor

Tx Enables PCITER(RW)-MBAR + 0x380C .................................................................................10-24

Tx Next Address PCITNAR(R) -MBAR + 0x3810 ........................................................................10-25

Tx Last Word PCITLWR(R) -MBAR + 0x3814 ............................................................................10-26

Tx Done Counts PCITDCR(R) -MBAR + 0x3818 .........................................................................10-26

Tx Status PCITSR(RWC) -MBAR + 0x381C .................................................................................10-27

Tx FIFO Data Register PCITFDR(RW) -MBAR + 0x3840 ...........................................................10-28

Tx FIFO Status Register PCITFSR(R/RWC) -MBAR + 0x3844 ...................................................10-28

Tx FIFO Control Register PCITFCR(RW) -MBAR + 0x3848 .......................................................10-29

Tx FIFO Alarm Register PCITFAR(RW) -MBAR + 0x384C ........................................................10-30

Tx FIFO Read Pointer Register PCITFRPR(RW) -MBAR + 0x3850 ............................................10-31

Tx FIFO Write Pointer Register PCITFWPR(RW) -MBAR + 0x3854 ..........................................10-31

Multi-Channel DMA Receive Interface ...................................................................................................10-31

Rx Packet Size PCIRPSR(RW) -MBAR + 0x3880 ........................................................................10-32

Rx Start Address PCIRSAR (RW)-MBAR + 0x3884 .....................................................................10-32

Rx Transaction Control Register PCIRTCR(RW) -MBAR + 0x3888 ............................................10-32

Rx Enables PCIRER (RW) -MBAR + 0x388C ...............................................................................10-34

Rx Next Address PCIRNAR(R) -MBAR + 0x3890 ........................................................................10-35

Rx Last Word PCIRLWR(R) -MBAR + 0x3894 ............................................................................10-35

RxDone Counts PCIRDCR(R) -MBAR + 0x3898 ..........................................................................10-36

Rx Status PCIRSR (R/sw1) -MBAR + 0x389C ..............................................................................10-36

Rx FIFO Data Register PCIRFDR(RW) -MBAR + 0x38C0 ..........................................................10-38

Rx FIFO Status Register PCIRFSR(R/sw1) -MBAR + 0x38C4 .....................................................10-38

Rx FIFO Control Register PCIRFCR(RW) -MBAR + 0x38C8 ......................................................10-39

Rx FIFO Alarm Register PCIRFAR(RW) -MBAR + 0x38CC .......................................................10-40

Rx FIFO Read Pointer Register PCIRFRPR(RW) -MBAR + 0x38D0 ...........................................10-40

Rx FIFO Write Pointer Register PCIRFWPR (RW) -MBAR + 0x38D4 ........................................10-41

PCI Bus Background ................................................................................................................................10-41

Basic Transfer Control ..............................................................................................................................10-42

PCI Transactions .......................................................................................................................................10-42

PCI Bus Commands ..................................................................................................................................10-44

Addressing ................................................................................................................................................10-45

Memory space addressing ..................................................................................................................10-45

I/O space addressing ..........................................................................................................................10-46

Configuration space addressing and transactions ..............................................................................10-46

Address decoding ...............................................................................................................................10-47

Priority Scheme ........................................................................................................................................10-48

Endian Translation ....................................................................................................................................10-49

Configuration Mechanism ........................................................................................................................10-51

Type 0 Configuration Translation ......................................................................................................10-51

Type 1 Configuration Translation ......................................................................................................10-53

Interrupt Acknowledge Transactions .................................................................................................10-53

Special Cycle Transactions ................................................................................................................10-53

Transaction Termination ...........................................................................................................................10-54

Reads from Local Memory .......................................................................................................................10-55

Local Memory Writes ...............................................................................................................................10-55

Data Translation .......................................................................................................................................10-55

Target Abort .............................................................................................................................................10-56

Latrule Disable .........................................................................................................................................10-56

Access Width ............................................................................................................................................10-57

MPC5200B Users Guide, Rev. 1

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Number

TOC-7

Table of Contents