Slice Timers; Slt Registers—Mbar + 0X0700 - Freescale Semiconductor MPC5200B User Manual

Slice Timers

Bit Name
17:19 OVF Represents how many times internal counter has rolled over. This is pertinent only during IC
mode and would represent an extremely long period of time between Input Events. However, if
Stop_Cont = 1 (indicating cumulative reporting of Input Events), this field could come into play.
Note: This field is cleared by any "sticky bit" status write in the 4 bit fields below (28, 29, 30, 31).
20:22 — Reserved
23 PIN Registered state of the I/O PIN (all modes). The IP bus Clock registers the state of the I/O input.
Valid, even if Timer is not enabled.
24:27 — Reserved
28 TEXP Timer Expired in Internal Timer mode. Cleared by writing 1 to this bit position. Also cleared if
Timer_MS is 000 (i.e., Timer not enabled). See Note.
29 PWMP PWM end of period occurred. Cleared by writing 1 to this bit position. Also cleared if Timer_MS
is 000 (i.e., Timer not enabled). See Note.
30 COMP OC reference event occurred. Cleared by writing 1 to this bit position. Also cleared if Timer_MS
is 000 (i.e., Timer not enabled). See Note.
31 CAPT IC reference event occurred. Cleared by writing 1 to this bit position. Also cleared if Timer_MS is
000 (i.e., Timer not enabled). See Note.
Note: To clear any of these bits, it is necessary to clear all of them. An F must be written to bits 28:31.
7.5 Slice Timers
Two Slice Timers are included to provide shorter term periodic interrupts. Each timer consists of a 24-bit counter with no prescale. Running
off the IP bus clock, each timer can generate interrupts from 7.75uS to 508mS in 30nS steps (based on 33MHz IP bus clock). The counters
count up from zero and expire/interrupt when they reach the programmed terminal count. They can be configured to automatically reset to
zero and resume counting or wait until the Status/Interrupt is serviced before beginning a new cycle.
The current count value can be read without disturbing the count operation. Each Slice Timer has a Status bit to indicate the Timer has expired.
If enabled, a CPU interrupt is generated at count expiration. Each Timer has a separate Interrupt. Slice Timer 0 represents CPU interrupt
Critical Level 2 and Slice Timer 1 represents Main Level 0 (which is hardwired to the core_smi pin). Clearing the Status and/or Interrupt is
accomplished by writing 1 to the Status bit, or disabling the Timer entirely with the Timer Enable (TE) bit.
As a safety, the Timer does not count until a Terminal Count value of greater than 255 is programmed into it. Also, writing a Terminal Count
value of 0 is converted to all 1s, resulting in a maximum duration timeout.
7.5.1 SLT Registers—MBAR + 0x0700
There are two SLT Timers. Each one uses four 32-bit registers. These registers are located at an offset from MBAR of 0x0700. Register
addresses are relative to this offset. Therefore, the actual register address is:
Hyperlinks to the Interrupt Controller registers are provided below:
SLT 0 Terminal Count Register
•
SLT 1 Terminal Count Register
•
SLT 0 Control Register
•
SLT 1 Control Register
•
SLT 0 Count Value Register (0x0708)
•
SLT 1 Count Value Register (0x0718)
•
SLT 0 Timer Status Register (0x070C)
•
SLT 1 Timer Status Register (0x071C)
•
7-62
(0x0700)
(0x0710)
(0x0704)
(0x0714)
Read Only
Read Only
Read Only
Read Only
MPC5200B Users Guide, Rev. 1
Description
MBAR + 0x0700 + register address
Freescale Semiconductor