Freescale Semiconductor MPC5200B User Manual page 564

• Data shift direction SICR[SHDIR], data shifted out LSB first if SICR[SHDIR] = 1 otherwise data shifted out MSB first if
SICR[SHDIR] = 0
In the Codec "Soft Modem" mode the PSC send only one data word per frame.
Frame Sync Polarity
Frame Sync
BitCLK
DATA
RX / TX
start of Frame
Table 15-79 shows an example how to configure the PSC1 as:
• PSC in Slave mode
• 16 bit "soft Modem" mode
• Data are sampled on the falling edge of BitClk
• FrameSync is low true
• MSB first, transfer starts with leading edge of FrameSync
• set the TFALARM level to 0x010, alarm occurs if 16 byte are in the TxFIFO
• set the RFALARM level to 0x00C, alarm occurs if 12 byte space in the RxFIFO
• enable TxRDY interrupt
Register
CR
SICR 0x02100000
RFALARM
TFALARM
IMR
Port_Config 0x00000006
CR
Table 15-80 shows an example how to configure the PSC2 as:
• PSC in Master mode
• 32bit "soft Modem" mode
• Data are sampled on the rising edge of BitClk
Freescale Semiconductor
frame sync width
delay of time slot 1
data length
frame length
Figure 15-9. "Soft Modem" Codec interface diagram
Table 15-79. 16-Bit "soft Modem"Slave Mode
Value
0x0A Disable the Tx and Rx part for configuration if the PSC was enabled by the work
before.
Select the 16 bit Codec mode, msb first, DTS1 = 0, slave mode
0x000C set the RFALARM level to 0x00C
0x0010 set the TFALARM level to 0x010
0x0100 enable TxRDY interrupt
Select the Pin-Muxing for PSC1 Codec mode, see
0x05 Enable Tx and Rx
MPC5200B Users Guide, Rev. 1
BitClk polarity
data bit shift direction
Setting
PSC Operation Modes
start of next Frame
Chapter 2, Signal Descriptions
15-53