Freescale Semiconductor MPC5200B User Manual page 658

Adress Offset
R
W
RESET:
Adress Offset
R
W
RESET:
Adress Offset
R
W
RESET:
Adress Offset
R
W
RESET:
Bit Name
0:7 AC[7:0]
READ: Anytime
WRITE: Anytime in initialization mode (INITRQ + 1 and INITAK = 1).
On reception, each message is written into the background receive buffer. The CPU is only signalled to read the message if it passes the criteria
in the identifier acceptance and identifier mask registers (accepted); otherwise, the message is overwritten by the next message (dropped).
The acceptance registers of the MSCAN are applied on the IDR0 to IDR3 registers of incoming messages in a bit-by-bit manner.
For extended identifiers, all four acceptance and mask registers are applied. For standard identifiers, only the first two (CANIDAR0/1 and
CANIDMR0/1) are applied.
Freescale Semiconductor
Table 19-23. MSCAN ID Acceptance Registers (4 - 7)
msb 0 1 2
0x930 / 0x9B0
AC7 AC6 AC5
0 0 0
msb 0 1 2
0x931 / 0x9B1
AC7 AC6 AC5
0 0 0
msb 0 1 2
0x934 / 0x9B4
AC7 AC6 AC5
0 0 0
msb 0 1 2
0x935 / 0x9B5
AC7 AC6 AC5
0 0 0
Acceptance Code—bits comprise a user defined sequence with which corresponding bits
of the related identifier register (IDRn) of the receive message buffer are compared. Result
of this comparison is then masked with the corresponding identifier mask register.
MPC5200B Users Guide, Rev. 1
Memory Map / Register Definition
3 4 5
CANIDR4
AC4 AC3 AC2 AC1
0 0 0
3 4 5
CANIDR5
AC4 AC3 AC2 AC1
0 0 0
3 4 5
CANIDR6
AC4 AC3 AC2 AC1
0 0 0
3 4 5
CANIDR7
AC4 AC3 AC2 AC1
0 0 0
Description
6 7 lsb
AC0
0 0
6 7 lsb
AC0
0 0
6 7 lsb
AC0
0 0
6 7 lsb
AC0
0 0
19-19