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16
17
R
W
RESET
0
0
Bits
Name
0:31
Last_Word
10.3.3.2.7
Rx Bytes Done Counts PCIRDCR(R) —MBAR + 0x3898
msb 0
1
R
W
RESET
0
0
16
17
R
W
RESET
0
0
Bits
Name
0:31
Bytes_Done
10.3.3.2.8
Rx Packets Done Counts PCIRPDCR(R) —MBAR + 0x38A0
msb 0
1
R
W
RESET
0
0
16
17
R
W
RESET
0
0
Freescale Semiconductor
18
19
20
21
22
0
0
0
0
0
This status register indicates the last 32-bit data fetched from the FIFO and is designed for
the case in which an abnormal PCI termination has corrupted the integrity of the FIFO data
(for that word).
2
3
4
5
6
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
This status register indicates the number of Bytes received since the start of a packet. It is
updated at the end of each successful PCI data beat. For normally terminated packets, the
Bytes_Done value and the Packet_Size values are equal. If continuous mode is active, the
Bytes_Done value reads 0 at the end of a successful packet and the Packets_Done field
is incremented.
2
3
4
5
6
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
MPC5200B Users Guide, Rev. 1
23
24
25
26
Last_Word
0
0
0
0
Description
7
8
9
10
Bytes_Done
0
0
0
0
23
24
25
26
Bytes_Done
0
0
0
0
Description
7
8
9
10
Packets_Done
0
0
0
0
23
24
25
26
Packets_Done
0
0
0
0
Registers
27
28
29
30
31 lsb
0
0
0
0
11
12
13
14
15
0
0
0
0
27
28
29
30
31 lsb
0
0
0
0
11
12
13
14
15
0
0
0
0
27
28
29
30
31 lsb
0
0
0
0
0
0
0
0
0
10-39
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