Freescale Semiconductor MPC5200B User Manual page 146

Bit Name
15 sys_pll_bypass
16 boot_rom_lf
17 boot_rom_type
18 boot_rom_size
19 boot_rom_swap
20 boot_rom_wait
21 ppc_msrip
22 —
23 boot_rom_mg
24 sys_pll_cfg_1
25 sys_pll_cfg_0
26 xlb_clk_sel
Freescale Semiconductor
bit=0:Normal mode. The SYS OSC clock input is multiplied up by the system PLL, then
the PLL VCO is divided down to produce internal clocks.
bit=1:The SYS OSC clock input is used directly, bypassing the system PLL. No
multiplication of the input frequency is performed, but the input frequency is divided to
produce internal clocks just as the system PLL VCO frequency would be. sys_pll_cfg_1
and sys_pll_cfg_0 are ignored.
Large Flash mode is selected
Latched pin value at reset.
bit=0:non-muxed boot ROM bus, single tenure transfer.
bit=1:muxed boot ROM bus, with address and data tenures, ALE and TS active.
Latched pin value at reset.
For non-muxed boot ROMs:
bit=0:8bit boot ROM data bus, 24bit max boot ROM address bus
bit=1:16bit boot ROM data bus, 16bit boot ROM address bus
For muxed boot ROMs:
boot ROM address is max 25 significant bits during address tenure.
bit=0:16bit ROM data bus
bit=1:32bit ROM data bus
Latched pin value at reset.
bit=0:no byte lane swap, same
endian ROM image
bit=1:byte lane swap, different
endian ROM image
Latched pin value at reset.
bit=0:4 PCI clocks of wait state
bit=1:48 PCI clocks of wait state
Latched pin value at reset.
microprocessor Boot Address/Exception table location.
bit=0:0000_0100 (hex)
bit=1:FFF0_0100 (hex)
Read Only. Do not write.
Most/Graphic Mode is selected as BOOT mode
Latched pin value at reset.
bit=0:No operation.
bit=1:Internal System PLL frequency multiplication ratio specified by sys_pll_cfg_0 is
doubled (24x, 32x). No net effect on any internal clocks, except that PLL VCO runs
twice as fast. Useful in low frequency applications to keep VCO frequency (f
above min, see MPC5200B Hardware Specification.
Latched pin value at reset.
bit=0: f =16x SYS_XTAL_IN Frequency
system
bit=1: f =12x SYS_XTAL_IN Frequency
system
Latched pin value at reset.
bit=0:XLB_CLK= f / 4
system
bit=1:XLB_CLK= f / 8
system
MPC5200B Users Guide, Rev. 1
Description
CDM Registers
)
vcosys
5-13