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Figure 9-6
shows a MUXed transaction type timing diagram.
PCI CLK
AD[31,27] (wr)
AD[30:28] (wr)
AD[26:25] (wr)
AD[24:0] (wr)
AD[31:0] (rd)
ALE
TS
CSx
OE
RW
ACK
NOTE:
1.
ACK can shorten the CS pulse width.
2.
Address should be latched with the rising edge of ALE.
9.5
Configuration
The LPC supports several options in terms of modes, address and data sizes, speed, and configuration which are described below.
9.5.1
Boot Configuration
After power-on reset (POR) the e300 processor accesses the local bus to fetch initial code sequences. Chip Select Boot (CS Boot) is dedicated
for this purpose. CS Boot and CS0 are physically the same pins. The difference is that CS Boot is impacted by the reset configuration and is
enabled after reset.
Several options are also available for boot code fetches. The boot configuration is determined during POR using the reset_configuration word.
The following boot code configuration options are available, see
•
MUXed or non-MUXed mode.
— In MUXed mode Data bus can be 16- or 32-bits wide.
— In non-MUXed Legacy mode Data bus can be 8- or 16-bits wide.
— In non-MUXed MOST Graphics mode Data bus can be 32-bits wide.
— In non-MUXed Large Flash modes Data bus can be 8- or 16-bits wide.
•
The number of wait states during boot can be 4 or 48 PCI bus clock cycles.
Freescale Semiconductor
TSIZ[0:2] bits
Bank[0:1] bits
Address[7:31]
Address tenure
Figure 9-6. Timing Diagram—MUXed Mode
Table 9-6.
MPC5200B Users Guide, Rev. 1
valid write Data
valid write Data
valid write Data
valid write Data
valid read Data
Data tenure
Configuration
9-9
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