Fec Registers—Mbar + 0X3000 - Freescale Semiconductor MPC5200B User Manual

FEC Registers—MBAR + 0x3000
Address
290 RMON_R_CRC_ALIGN
294 RMON_R_UNDERSIZE
298 RMON_R_OVERSIZE
29C
2A0
2A4 RMON_R_RESVD_0
2A8
2AC RMON_R_P65TO127
2B0 RMON_R_P128TO255
2B4 RMON_R_P256TO511
2B8 RMON_R_P512TO1023
2BC RMON_R_P1024TO2047
2C0 RMON_R_P_GTE2048
2C4 RMON_R_OCTETS
2C8
2CC IEEE_R_FRAME_OK
2D0
2D4
2D8
2DC
2E0 IEEE_R_OCTETS_OK
2E4–2FC
300–3FF
14.5 FEC Registers—MBAR + 0x3000
The FEC uses 37 32-bit registers. These registers are located at an offset from MBAR of 0x3000. Register addresses are relative to this offset.
Therefore, the actual register address is
Hyperlinks to the FEC registers are provided below:
14-10
Table 14-8. MIB Counters (continued)
Mnemonic
RMON Rx Packets with CRC/Align error
RMON Rx Packets less than 64Bytes, good CRC
RMON Rx Packets greater than MAX_FL bytes, good CRC
RMON_R_FRAG RMON Rx Packets less than 64Bytes, bad CRC
RMON_R_JAB RMONRxPackets greater than MAX_FL bytes, bad CRC
Reserved
RMON_R_P64 RMON Rx 64Byte packets
RMON Rx 65 to 127Byte packets
RMON Rx 128 to 255Byte packets
RMON Rx 256 to 511Byte packets
RMON Rx 512 to 1023Byte packets
RMON Rx 1024 to 2047Byte packets
RMON Rx packets with greater than 2048Bytes
RMON Rx Octets
IEEE_R_DROP Count of frames not counted correctly
Frames received OK
IEEE_R_CRC Frames received with CRC error
IEEE_R_ALIGN Frames received with alignment error
IEEE_R_MACERR Rx FIFO overflow count
R_FDXFC Flow Control Pause frames received
Octet count for frames received without error
rsvd Reserved
rsvd Reserved
MBAR + 0x3000 + register address
MPC5200B Users Guide, Rev. 1
Description
Freescale Semiconductor