Bdlc Module Initialization; Initialization Sequence; Basic Bdlc Module Transmit Flowchart - Freescale Semiconductor MPC5200B User Manual

C
For interrupt driven systems,
this marks the beginning of the
transmit section of the BDLC
module interrupt service
routine
Go to BDLC module
BREAK/Error Handling
Routine
B
Jump to BDLC module
Receive Routine
NOTE: The EOF and CRC Error interrupts
are handled in the BDLC module Receive
Routine
20.8.9

BDLC Module Initialization

This section includes sample flows for initializing the BDLC module and using it to transmit and receive messages.
20.8.9.1

Initialization Sequence

To initialize the BDLC module, the user should first write the desired data to the configuration bits. The BDLC module should then be taken
out of digital and analog loopback mode and enabled. Exiting from loopback mode will entail change of state indications in the BDLC State
Vector Register which must be dealt with. Once this is complete, CPU interrupts can be enabled (if desired), and then the BDLC module is
capable of SAE J1850 serial network communication. For an illustration of the sequence necessary for initializing the BDLC module, refer
to Figure 20-20.
Freescale Semiconductor
Enter BDLC module Transmit
Routine
Write first message
byte to be transmitted
into DLCBDR
Yes
Is DLCBSVR = $00?
No
Yes
Is DLCBSVR = $1C?
(Invalid Symbol)
No
B
Yes
Is DLCBSVR = $14?
(LOA)
No
No
Is DLCBSVR = $10?
(TDRE)
Yes
Load next byte to be
transmitted into DLCBDR
(clears TDRE)
A
Figure 20-19. Basic BDLC Module Transmit Flowchart
MPC5200B Users Guide, Rev. 1
A
No
Is this the last
byte?
Yes
Set TEOD bit
in DLCBCR2
Yes
IFR Received?
No
Once BDLC module detects
EOF, transmit
attempt is complete
Yes
Attempt another
transmission?
No
Exit BDLC module Transmit
Routine
Functional Description
Jump to Receive IFR
Handling Routine
C
20-47