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10.3.3.2.4
Rx Enables PCIRER (RW) —MBAR + 0x388C
msb 0
1
R
RC
RF
W
RESET
0
0
16
17
R
Reserved
W
RESET 0
0
Bits
Name
0
Reset
Controller
(RC)
1
Reset
FIFO
(RF)
2
FE
3
Continuous
mode
(CM)
4
Bus error
Enable
(BE)
5:6
Reserved
7
Master
Enable
(ME)
8:9
Reserved
10
FIFO Error
Enable
(FEE)
Freescale Semiconductor
2
3
4
5
6
FE
CM
BE
Reserved
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
User writes this bit high to put Receive Controller in a reset state. Note that other register
bits are not affected. This Reset is intended for recovery from an error condition or to reload
the Start Address when Continuous mode is selected. This Reset bit does not prohibit
register access but it must be negated in order to initiate a Restart sequence (i.e. writing the
Packet_Size register). If it is used to reload a Start Address then the Start_Add register must
be written prior to asserting this Reset bit.
The FIFO will be reset and flushed of any existing data when set high. The Reset Controller
bit and the Reset FIFO bit operate independently, but clearly both must be low for normal
operation.
Flush enable. This is an important bit which causes a flush signal to be generated to the
Receive FIFO Controller when the end of the current packet occurs. This Flush is necessary
to insure that the Multi-Channel DMA will get all data left in the Receive FIFO. FE is active
high.
User writes this bit high to activate Continuous mode. In Continuous mode the Start_Add
value is ignored at each packet restart and the PCI address is auto-incremented from one
packet to the next. Also, the Packets_Done status byte will become active, indicating how
many packets have been received since the last Reset Controller condition. If the
Continuous bit is low, software is responsible for updating the Start_Add value at each
packet Restart.
User writes this bit high to enable Bus Error indications.
PCIRSR (R/sw1) —MBAR + 0x389C
since illegal Slave bus accesses are not destructive to register contents, although it may
indicate broken software. Note that this bit does not affect interrupt generation.
Unused. Software should write zero to these bits.
This is the Receive Controller master enable signal. User must write it high to enable
operation. It can be toggled low to permit out-of-order register updates prior to generating
a Restart sequence (in which case transmission will begin when Master Enable is written
back high), but it should not be used as such in Continuous mode because it has the side
effect of resetting the Packets_Done status counter.
Unused. Software should write zero to these bits.
User writes this bit high to enable CPU Interrupt generation in the case of FIFO error
termination of a packet transmission. It may be desirable to mask CPU interrupts in the case
that Multi-Channel DMA is controlling operation, but in such a case software should poll the
status bits to prevent a possible lock-up condition.
MPC5200B Users Guide, Rev. 1
7
8
9
10
ME
Reserved
FEE
0
0
0
0
23
24
25
26
27
0
0
0
0
0
Description
Section 10.3.3.2.9, Rx Status
for Bus Error descriptions. Normally this bit will be 0
Registers
11
12
13
14
15
SE
RE
TAE
IAE
NE
0
0
0
0
28
29
30
31 lsb
0
0
0
0
0
10-37
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