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For interrupt driven systems,
this marks the beginning of the
transmit section of the BDLC
module interrupt service
routine
Go to BDLC module
BREAK/Error Handling
Routine
B
Jump to BDLC module
Receive Routine
NOTE: The EOF and CRC Error interrupts
are handled in the BDLC module Receive
Routine
20.8.5
Receiving A Message
The design of the BDLC module makes it especially easy to use for receiving messages off of the SAE J1850 bus. When the first byte of a
message comes in, the BDLC State Vector Register will indicate to the CPU that a byte has been received. As each successive byte is received,
that will in turn be reflected in the BDLC State Vector Register. When the message is complete and the EOF has been detected on the bus, the
BDLC State Vector Register will reflect this, indicating that the message is complete.
The basic steps required for receiving a message from the SAE J1850 bus are outlined below. For more information on receiving IFR bytes,
refer to
Section 20.8.7, Receiving An In-Frame Response
Freescale Semiconductor
Enter BDLC module Transmit
Routine
C
Write first message
byte to be transmitted
into DLCBDR
Yes
Is DLCBSVR = $00?
No
Yes
Is DLCBSVR = $1C?
(Invalid Symbol)
No
Yes
Is DLCBSVR = $14?
(LOA)
No
Is DLCBSVR = $10?
(TDRE)
Yes
Load next byte to be
transmitted into DLCBDR
(clears TDRE)
A
Figure 20-13. Basic BDLC Transmit Flowchart
(IFR).
MPC5200B Users Guide, Rev. 1
A
No
Is this the last
byte?
Yes
Set TEOD bit
in DLCBCR2
IFR Received?
No
B
Once BDLC module detects
EOF, transmit
attempt is complete
No
Attempt another
transmission?
No
Exit BDLC module Transmit
Routine
Functional Description
Yes
Jump to Receive IFR
Handling Routine
Yes
C
20-33
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