Freescale Semiconductor MPC5200B User Manual page 458

16 17
R
W
RESET: 0 0
Bit Name
0:31 Value2
13.15.31 SDMA Debug Module Control Register—MBAR + 0x1278
msb 0 1
R
W
RESET: 0 0
16 17
R AA B
W
RESET: 0 0
Bit Name
0:15 Block Tasks
16 AA
17 B
18:20 Comparator
Type 1
21:23 Comparators
Type 2
24 and / or
Freescale Semiconductor
18 19 20 21 22
0 0 0 0 0
Debug Module Comparator 2 Value.
Table 13-32. SDMA Debug Module Control Register
2 3 4 5 6
0 0 0 0 0
18 19 20 21 22
Comparator Type 1 Comparator Type 2
0 0 0 0 0
Specify for each of tasks 15-0, whether to block that task with detection of a breakpoint (bit
0 halts TASK 15, bit 1 halts TASK 14, etc)
0 Do not block task
1 Block the task
AutoArm—specifies whether or not the triggered bit dbgStatusReg[16] will be
automatically reset to 0 following the saving of context for a breakpoint. This bit is set to 0
at reset.
0 Triggered bit will not be automatically reset
1 Triggered bit will be automatically reset
Breakpoint—This bit specifies whether or not to take a breakpoint. This bit is set to 0 at
reset.
0 Disable breakpoints
1 Enable breakpoints
Comparator 1 type—These bits specify the type of data that has been loaded into
comparator 1; refer to Table 13-33
Comparator 2 type—These bits specify the type of data that has been loaded into
comparator 2; refer to Table 13-34
AND/OR—This specifies what type of operation is to be used with the comparators. This
bit is set to 0 at reset.
0 Indicates an OR'ing of the comparators
1 Indicates an AND'ing of the comparators
MPC5200B Users Guide, Rev. 1
BestComm DMA Registers—MBAR+0x1200
23 24 25 26 27
Value2
0 0 0 0
Description
7 8 9 10 11
Block Tasks
0 0 0 0
23 24 25 26 27
and/ EU breakpoints
or
0 0 0 0
Description
for the bit encoding.
for the bit encoding.
28 29 30 31 lsb
0 0 0 0 0
12 13 14 15
0 0 0 0 0
28 29 30 31 lsb
E I B
0 0 0 0 0
13-25