Freescale Semiconductor MPC5200B User Manual page 180

Bits Name
27 PEa17
28 PEa18
29:30 —
31 PEa21
7.2.4.16 ICTL IRQ Interrupt Emulation All Register—MBAR + 0x0548
msb 0 1
R Reserved
W
RESET: 0 0
16 17
R
W
RESET: 0 0
Bits Name
0:3 —
— IRQEa[x]
4 IRQEa0
5 IRQEa1
6 IRQEa2
7 IRQEa3
8:31 —
Note:
1. The emulation is only possible if the IRQ pins are externally pulled down. Otherwise the OR between the external pin
values and the IRQEa[x] bits is whole the time one.
Freescale Semiconductor
CAN1
CAN2
Reserved
XLB Arbiter
Table 7-19. ICTL IRQ Interrupt Emulation All Register
2 3 4 5 6
IRQEa
0 0 0 0 0
18 19 20 21 22
0 0 0 0 0
Reserved
This register provides a way for software to emulate the assertion of a particular external
interrupt pin. The actual interrupt is the OR of the normal interrupt source and each of these
IRQEa[x] bits.
This register represents the four IRQ inputs. This register is redundant with IICTL Main
Interrupt Emulation All Register for IRQ1-3 but is the only source to emulate IRQ0. It provides
a single register with which to test and develop an ISR for the external interrupt sources.
Each bit operates as if it were the pin itself, i.e. edge sensitive operation would require
multiple test writes to create the emulation of a pulsing input. See Note
IRQ[0] input pin emulation
IRQ[1] input pin emulation
IRQ[2] input pin emulation
IRQ[3] input pin emulation
Reserved
MPC5200B Users Guide, Rev. 1
Description
7 8 9 10 11
0 0 0 0
23 24 25 26 27
Reserved
0 0 0 0
Description
Interrupt Controller
12 13 14 15
Reserved
0 0 0 0 0
28 29 30 31 lsb
0 0 0 0 0
1
7-21