Freescale Semiconductor MPC5200B User Manual page 527

PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00
Bit Name
0:19 RB AC97 (0:19)—Received data—AC97 data must be read one complete sample at a time, where
(AC97) all samples except time slot #0 are 20 bits. Time slot #0 data is in bits 0:15. Bit 20 is 1 in the first
or sample of a new frame.
0:31
Bit 20 contains the "Start of Frame Indicator" SOF:
(other)
The bits [21:31] are reserved at this mode.
UART/SIR/MIR/FIR/Codec8 (0:31)—Received data—For these modes, data can be read 1, 2
or 4 bytes at a time. For one byte at a time, all bytes must be read from bits 0:7. For 2 bytes at
a time, data must be read from bits 0:15. Lower-bit data was received before upper-bit data.
Codec16 (0:31)—Received data—For these modes, data can be read 2 or 4 bytes at a time.
For 2 bytes at a time, data must be read from bits 0:15. Lower-bit data was received before
upper-bit data.
Codec24 (0:23)—Received data—For these modes, data must be read 4 bytes at a time. The
lower 24 bits contain the received data word.
Codec32 (0:31)—Received data—For these modes, data must be read 4 bytes at a time.
15.2.7 Tx Buffer Register (0x0C)
Data is written to the Tx FIFO by writing to this write-only register. The Tx FIFO size is 512 bytes. To write data to the TX FIFO you can
also use the TFDATA register, see
Please note that the TX FIFO access via TB address will be blocked if the PSC was set to UART or
SIR mode and the transmitter is disabled. The access via TFDATA will be never blocked.
Table 15-20. Tx Buffer Register (0x0C) for UART/SIR/MIR/FIR/Codec8/16/32 Modes
msb 0 1
R
W
RESET: 0 0
16 17
R
W
RESET: 0 0
msb 0 1
R
W
RESET: 0 0
16 17
R
W TB[16:19]
RESET: 0 0
15-16
0 = RB[0:19] is not the first sample in the frame.
1 = RB[0:15] is the first sample in a new frame. The number 0 slot is called the TAG slot.
TB
—
Section 15.2.38, Tx FIFO Data (0x80)—TFDATA.
2 3 4 5 6
0 0 0 0 0
18 19 20 21 22
0 0 0 0 0
Table 15-21. TX Buffer Register (0x0C) for AC97) Modes
2 3 4 5 6
0 0 0 0 0
18 19 20 21 22
SOF
0 0 0 0 0
MPC5200B Users Guide, Rev. 1
Description
NOTE
7 8 9 10
Used by Rx Buffer
TB[0:15]
0 0 0 0
23 24 25 26
Used by Rx Buffer
TB[16:31]
0 0 0 0
7 8 9 10
Used by Rx Buffer
TB[0:15]
0 0 0 0
23 24 25 26
Used by Rx Buffer
Reserved
0 0 0 0
11 12 13 14 15
0 0 0 0
27 28 29 30 31 lsb
0 0 0 0
11 12 13 14 15
0 0 0 0
27 28 29 30 31 lsb
0 0 0 0
Freescale Semiconductor
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