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Bit
Name
0–6
—
7
ddr_mode
8–14
—
15
xlb_clk_sel
16–22
—
23
ipb_clk_sel
24–29
—
30-31
pci_clk_sel
The clock ratio should only be changed if no module, which is clocked by the IPB and/or PCI clock,
is currently running. Suggestion is to change the clock ratio during the boot time only.
5.5.5
CDM 48MHz Fractional Divider Configuration Register—MBAR + 0x0210
The CDM 48MHz Fractional Divider Configuration Register contains the control bits used in the 48MHz fractional divider.
Table 5-12. CDM 48MHz Fractional Divider Configuration Register
msb 0
1
R
Reserved
Write 0
W
RESET:
0
0
16
17
R
cfgd_p3_cnt
W
RESET:
0
0
Freescale Semiconductor
Reserved for future use. Write 0.
SDRAM Controller DDR memory mode, read-only.
bit=0:SDRAM Controller configured for SDR SDRAM (single data rate)
bit=1:SDRAM Controller configured for DDR SDRAM (double data rate)
This register location is a read-only status bit; write 0. The controlling register is in the
SDRAM Controller register map. In the CDM this bit determines the frequency and phase
of memory read clock.
Reserved for future use. Write 0.
XLB Clock Frequency
bit=0:XLB CLK = f
system
bit=1:XLB CLK = f
system
This register location is a read-only status bit. The controlling register is the POR
Configuration register - cdm configuration register [26].
Reserved for future use. Write 0.
IPB Clock Select
bit=0:IPB CLK = XLB_CLK
bit=1:IPB CLK = XLB_CLK/2
Reserved for future use. Write 0.
PCI Clock Select
00–PCI_CLK = IPB_CLK
01–PCI_CLK = IPB_CLK/2
10–PCI_CLK = XLB_CLK/4
See also
Table 5-3
and
Table
2
3
4
5
0
0
0
0
18
19
20
21
22
cfgd_p2_cntt
0
0
0
0
MPC5200B Users Guide, Rev. 1
Description
/4
/8
5-4.
NOTE
6
7
8
9
10
0
0
0
0
0
23
24
25
26
cfgd_p1_cnt
0
0
0
0
0
CDM Registers
11
12
13
14
Reserved
Write 0
0
0
0
0
27
28
29
30
cfgd_p0_cnt
0
0
0
0
15
fd_en
0
31 lsb
0
5-15
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