Freescale Semiconductor MPC5200B User Manual page 550

Bit Name
0:3 —
4:7 Frame[3:0]
8 —
9 Error
10 UF
11 OF
12 FR
13 FULL
14 ALARM
15 EMPTY
15.2.32 Rx FIFO Control (0x68)—RFCNTL
msb 0
R Reserved
W
RESET: 0
Bit Name
0:1 —
2 WFR
3 COMP
4 FRAME
5:7 GR[2:0]
15.2.33 Rx FIFO Alarm (0x6E)—RFALARM
msb 0 1
R Reserved
W
RESET: 0 0
Freescale Semiconductor
PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00
Reserved
Frame indicator. Not applicable to PSC FIFO's, since the PSCs do not recognize frame
formats in the serial data stream.
Reserved
FIFO error. A FIFO error has occurred due to either underflow, overflow, or read or write
pointer out of bounds.This bit is cleared by writing a '1' to it.
Underflow. The read pointer has surpassed the write pointer due to the FIFO having been
read when it contained no data. This bit is cleared by writing a '1' to it.
Overflow. The write pointer has surpassed the read pointer due to the FIFO having been
written when it was already completely full of data. This bit is cleared by writing a '1' to it.
Frame ready. Not applicable to PSC FIFO's, since the PSCs do not recognize frame
formats in the serial data stream.
Full. The FIFO is completely full of data.
The FIFO is requesting service from either BestComm or CPU. See
FIFO Alarm (0x6E)—RFALARM
FIFO Empty. The FIFO is completely empty.
Table 15-60. Rx FIFO Control (0x68)
1 2
WFR
0 0
Reserved
Write frame. Not applicable to PSC FIFOs, since the PSCs do not recognize frame formats in
the serial data stream.
Re-enable requests on frame transmission completion. Not applicable to PSC FIFOs, since
the PSCs do not recognize frame formats in the serial data stream.
Frame mode enable. THIS BIT MUST BE CLEARED BY WRITING A '0' TO IT, since the PSCs
do not recognize frame formats in the serial data stream.
Last transfer granularity. Amount of data remaining in the Rx FIFO at which the ALARM bit in
the status register will go low/inactive. See
Table 15-61. Rx FIFO Alarm (0x6E)
2 3 4 5 6
0 0 0 0 0
MPC5200B Users Guide, Rev. 1
Description
for a detailed description.
3 4
COMP FRAME
0 1
Description
Section 15.4, PSC FIFO System
7 8 9 10
ALARM
0 0 0 0
Section 15.2.33, Rx
5 6 7 lsb
GR[2:0]
0 0
for details.
11 12 13 14
0 0 0 0
1
15 lsb
0
15-39