Freescale Semiconductor MPC5200B User Manual page 623

2
I C Interface Registers
2
18.3.1 I C Address Register (MADR)—MBAR + 0x3D00 / 0x3D40
msb 0 1
R
W
RESET: 0 0
16 17
R
W
RESET: 0 0
Bit Name
0:6 ADR[7:1]
7:31 —
2
18.3.2 I C Frequency Divider Register (MFDR)—MBAR + 0x3D04 / 0x3D44
msb 0 1
R
W
RESET: 0 0
16 17
R
W
RESET: 0 0
Bit Name
0:1 FDR[7:6]
2:7 FDR[5:0]
8:31 —
The Frequency Divide register determines the SCL or serial bit-clock frequency. Table 18-4 must be used to select FDR bits that produce an
appropriate SCL. The following relationships (1) through (4), which illustrate the connection between Table 18-4 and the signals in the I2C
timing specification, are as follows:
SCL (in kHz) = (1/1000) * [system clock speed (in Hz)] / (SCL period) (1)
SDA Hold Time (in us) = 1000 * (SDA Hold / SCL Period) / [SCL (in kHz)] (2)
SCL Hold Time of START (in us) = 1000 * (SDA Hold of START / SCL Period) / [SCL (in kHz)] (3)
SCL Hold Time of STOP (in us) = 1000 * (SDA Hold of STOP / SCL Period) / [SCL (in kHz)] (4)
The following figure illustrates the relationship between system clock and the I2C signals.
18-6
Table 18-2. I
2 3 4 5 6
ADR[7:1]
0 0 0 0 0
18 19 20 21 22
0 0 0 0 0
Bits 0 to 6 contains the address I
Note: This is not the address sent on the bus during address transfer.
Reserved
2
Table 18-3. I C Frequency Divider Register
2 3 4 5 6
FDR[7:0]
0 0 0 0 0
18 19 20 21 22
0 0 0 0 0
These 2 bits act as a prescale divider of the input module clock.
This field is used to prescale the clock for bit-rate selection.
Reserved
MPC5200B Users Guide, Rev. 1
2
C Address Register
7 8 9 10
0 0 0 0
23 24 25 26
Reserved
0 0 0 0
Description
2
C responds to, when addressed as a slave.
7 8 9 10
0 0 0 0
23 24 25 26
Reserved
0 0 0 0
Description
11 12 13 14
Reserved
0 0 0 0
27 28 29 30
0 0 0 0
11 12 13 14
Reserved
0 0 0 0
27 28 29 30
0 0 0 0
Freescale Semiconductor
15
0
31 lsb
0
15
0
31 lsb
0