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Host Control (HC) Operational Registers
12.4.3.3
USB HC Control Head Endpoint Descriptor Register —MBAR + 0x1020
The HC Control Head Endpoint Descriptor register contains the physical address of the first endpoint descriptor of the Control list.
Table 12-9. USB HC Control Head Endpoint Descriptor Register
msb 0
1
R
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Bits
Name
0:27
CHED
28:31
—
12.4.3.4
USB HC Control Current Endpoint Descriptor Register —MBAR + 0x1024
The HC Control Current Endpoint Descriptor register contains the physical address of the current control list endpoint descriptor.
Table 12-10. USB HC Control Current Endpoint Descriptor Register
msb 0
1
R
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Bits
Name
0:27
CCED
28:31
—
12.4.3.5
USB HC Bulk Head Endpoint Descriptor Register—MBAR + 0x1028
The HC Head Endpoint Descriptor register contains the physical address of the first bulk list endpoint descriptor.
12-14
2
3
4
5
6
0
0
0
0
0
18
19
20
21
22
CHED
0
0
0
0
0
ControlHeadED—HC traverses the control list starting with the HcControlHeadED pointer.
Content is loaded from HCCA during HC initialization.
Reserved
2
3
4
5
6
0
0
0
0
0
18
19
20
21
22
CCED
0
0
0
0
0
ControlCurrentED—pointer is advanced to next ED after serving the present one. HC
continues processing the list from where it left off in the last frame. When it reaches the control
list end, HC checks the HcCommandStatus ControlListFilled.
•
If set, CCED copies HcControlHeadED content to HcControlCurrentED and clears bit.
•
If not set, it does nothing.
HCD is allowed to modify this register only when the ControlListEnable of HcControl is cleared.
When set, HCD only reads the instantaneous value of this register. Initially, this is set to 0 to
indicate the end of the Control List.
Reserved
MPC5200B Users Guide, Rev. 1
7
8
9
10
11
CHED
0
0
0
0
23
24
25
26
27
0
0
0
0
Description
7
8
9
10
11
CCED
0
0
0
0
23
24
25
26
27
0
0
0
0
Description
12
13
14
15
0
0
0
0
0
28
29
30
31 lsb
Reserved
0
0
0
0
0
12
13
14
15
0
0
0
0
0
28
29
30
31 lsb
Reserved
0
0
0
0
0
Freescale Semiconductor
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