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Registers
Bits
Name
10
Bus Error
type 1
(BE1)
11
FIFO Error
(FE)
12
System
Error
(SE)
13
Retry Error
(RE)
14
Target Abort
(TA)
15
Initiator
Abort
(IA)
16:31
Reserved
10.3.3.1.10 Tx FIFO Data Register PCITFDR(RW) —MBAR + 0x3840
msb 0
1
R
W
RESET
16
17
R
W
RESET
10-30
This flag is set whenever a Slave bus transaction attempts to read a Reserved register (an
entire 32-bit register, not just a Reserved bit or byte). This flag bit is set regardless of the Bus
error Enable bit (BE). If software is polling this Byte and wishes to disregard this error it must
mask this bit out.
This flag is set whenever the Transmit FIFO asserts its FIFO Error output. A CPU interrupt will
be generated if the FIFO Error Enable (FEE) bit is set. The source of the error must be
determined by reading the FIFO Error status register. Also, the error condition must be cleared
at the FIFO prior to clearing this Sticky bit or this flag will continue to assert.
This flag is set in response to the Transmit Controller entering an illegal state. A CPU interrupt
will be generated if the System error Enable (SE) bit is set. In normal operation this should
never occur. The only recovery is to assert the Reset Controller bit, PCITER[RC], and clear
this flag.
This flag is set if Max_Retries is set to a finite value (0x01 to 0xff) and the PCI transaction has
performed retries in excess of the setting. A CPU interrupt will be generated if the Retry error
Enable (RE) bit is set. The retry counter is reset at the beginning of each transaction (i.e. it is
not cumulative throughout a packet) and would generally indicate a broken or improperly
accessed Target.
This flag bit is set if the PCI controller has issued a Target Abort (which means the addressed
PCI Target has signalled an Abort). A CPU interrupt will be generated if the Target Abort
Enable (TAE) bit is set. It is up to application software to query the Target's status register and
determine the source of the error. The coherency of the Transmit FIFO data and the Transmit
Controller's status registers (Next_Address, Bytes_Done, etc.) should remain valid.
This flag bit is set if the PCI controller issues an Initiator Abort flag. This indicates that no Target
responded but further status information can be read from the PCI Configuration interface. A
CPU interrupt will be generated if the Initiator Abort error Enable (IAE) bit is set. The coherency
of the Transmit FIFO data and the Transmit Controller's status registers (Next_Address,
Bytes_Done, etc.) should remain valid.
Unused. Software should write zero to these bits.
2
3
4
5
6
uninitialized random 16 bit value
18
19
20
21
22
uninitialized random 16 bit value
MPC5200B Users Guide, Rev. 1
Description
7
8
9
10
FIFO_Data_Word
23
24
25
26
FIFO_Data_Word
11
12
13
14
15
27
28
29
30
31 lsb
Freescale Semiconductor
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