Freescale Semiconductor MPC5200B User Manual page 524

msb 0
R
W Reserved
RESET: 0
Bit Value Command
0 —
1:3 000 no command —
001 reset mode
010
011
transmitter
100 reset error
101 reset break
110 start break
111 stop break
Freescale Semiconductor
PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00
Table 15-16. Command Register (0x08) for all Modes
1 2
MISC
0 0
Reserved
Causes MR register address to point to MR1.
register
pointer
reset Immediately disables receiver, clears SR[FFULL,RxRDY], and re-initializes
receiver receiver FIFO pointer. No other registers are altered. Because it places the
receiver in a known state, use this command instead of RECEIVER DISABLE
when reconfigure the receiver.
reset In UART mode, immediately disables Tx and clears SR[TxEMP,TxRDY]. No
other registers are altered. Because it places Tx in a known state, use this
command instead of TRANSMITTER DISABLE when reconfigure transmitter.
In Codec mode, URERR is not cleared by this soft reset. It is cleared the same
way as the Rx overflow bit, by a RESET ERROR STATUS command.
In UART mode, clears ISR[RB,FE,PE,ORERR].
status
In Codec mode, command clears ISR[ORERR, URERR, DEOF, CMD_SEND,
DATA_OVR, DATA_VALID, UNEX_RX_SLOT]]
Clears the delta break bit, ISR[DB]. Command has no effect in Codec mode.
change
interrupt
Forces TxD low
• If Tx is empty, break may be delayed up to one bit-time.
• If Tx is active, break starts when character transmission completes.
Break is delayed until any character in Tx shift register is sent. Any character in
Tx holding register is sent after the break. Tx must be enabled for command to be
accepted. This command ignores the CTS state and has no effect in Codec mode.
Causes TxD to go high (mark) within two bit-times. Any characters in the Tx buffer
are sent.
MPC5200B Users Guide, Rev. 1
3 4 5
Reserved
TC
0 0 0
Description
6 7 lsb
RC
0 0
15-13