Ata Rx/Tx Fifo Control Register—Mbar + 0X3A44; Ata Rx/Tx Fifo Alarm Register—Mbar + 0X3A48 - Freescale Semiconductor MPC5200B User Manual

ATA Register Interface
Bits Name
10 UF
11 OF
12 Full
13 HI
14 LO
15 Emty
16:31 —
11.3.2.3 ATA Rx/Tx FIFO Control Register—MBAR + 0x3A44
msb 0 1
R Reserved
W
RESET: 0 0
16 17
R
W
RESET: 0 0
Bits Name
0:1 —
2 WFR
3:4 —
5:7 GR
8:31 —
11.3.2.4 ATA Rx/Tx FIFO Alarm Register—MBAR + 0x3A48
msb 0 1
R
W
RESET: 0 0
11-10
UnderFlow—flag indicates read pointer has surpassed the write pointer. FIFO was read
beyond empty. Resetting FIFO clears this condition; writing 1 to this bit clears flag.
OverFlow—flag indicates write pointer surpassed read pointer. FIFO was written beyond full.
Resetting FIFO clears this condition; writing 1 to this bit clears flag.
FIFO full—this is NOT a sticky bit or error condition. Full indication tracks with FIFO state.
High—FIFO requests attention, because high level alarm is asserted. To clear this condition,
FIFO must be read to a level below the setting in granularity bits.
Low—FIFO requests attention, because Low level alarm is asserted. To clear this condition,
FIFO must be written to a level in which the space remaining is less than the granularity bit
setting.
FIFO empty—this is NOT a sticky bit or error condition. Full indication tracks with FIFO state.
Reserved
Table 11-15. ATA Rx/Tx FIFO Control Register
2 3 4 5 6
WFR Reserved GR
0 0 0 0 0
18 19 20 21 22
0 0 0 0 0
Reserved
Write End of Frame (EOF) This bit should remain low.
Reserved
Granularity—bits control high "watermark" point at which FIFO negates Alarm condition (i.e.,
request for data). It represents the number of free bytes times 4.
000 = FIFO waits to become completely full before stopping data request.
001 = FIFO stops data request when only one long word of space remains.
Reserved
Table 11-16. ATA Rx/Tx FIFO Alarm Register
2 3 4 5 6
0 0 0 0 0
MPC5200B Users Guide, Rev. 1
Description
7 8 9 10 11
0 0 0 0
23 24 25 26 27
Reserved
0 0 0 0
Description
7 8 9 10 11
Reserved
0 0 0 0
12 13 14 15
Reserved
0 0 0 0 0
28 29 30 31 lsb
0 0 0 0 0
12 13 14 15
0 0 0 0 0
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