Freescale Semiconductor MPC5200B User Manual page 179

Interrupt Controller
7.2.4.15 ICTL Peripheral Interrupt Emulation All Register—MBAR + 0x0544
msb 0 1
R
W
RESET: 0 0
16 17
R
W
RESET: 0 0
Bits Name
0:7 —
— PEa[x]
8 PEa23
9 PEa22
10 PEa0
11 PEa1
12 PEa2
13 PEa3
14 PEa4
15 PEa5
16 PEa6
17 PEa7
18 PEa8
19 PEa9
20 PEa10
21 PEa11
22 PEa12
23 PEa13
24 PEa14
25 PEa15
26 PEa16
7-20
Table 7-18. ICTL Peripheral Interrupt Emulation All Register
2 3 4 5 6
Reserved
0 0 0 0 0
18 19 20 21 22
PEa
0 0 0 0 0
Reserved
This register provides a way for software to emulate the assertion of a particular Peripheral
interrupt. The actual interrupt is the OR or the normal interrupt source and each of these test
register bits. The order is exactly the same as the PSa in ICTL Peripheral Interrupt Status All
Register. The PEa[x] bits ARE masked by the Per_Mask setting, so they operate as much as
possible as the real interrupt source. Test assertion of a Periperhal source will cause HI-int
or LO-int indications which will be reflected in the Main or Critical status registers. If relying
on PEa[x] assertion/negation to emulate and test an ISR routine it is important to disable all
source modules so that real source interrupts will not disturb the test generated interrupt.
BestComm LocalPlus
BDLC
BestComm interrupt source
PSC1
PSC2
PSC3
PSC6
Ethernet
USB
ATA
PCI Control module
PCI SC Initiator Rx
PCI SC Initiator Tx
PSC4
PSC5
SPI modf
SPI spif
2
I C1
2
I C2
MPC5200B Users Guide, Rev. 1
7 8 9 10 11
0 0 0 0
23 24 25 26 27
0 0 0 0
Description
12 13 14 15
PEa
0 0 0 0 0
28 29 30 31 lsb
Reserved PEa21
0 0 0 0 0
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