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General Purpose I/O (GPIO)
Bit
Name
0:7
SIGPIOE
8:31
—
7.3.2.1.10
GPS GPIO Simple Interrupt Open-Drain Emulation Register —MBAR + 0x0B24
Table 7-30. GPS GPIO Simple Interrupt Open-Drain Emulation Register
msb 0
1
R
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Bit
Name
0:7
SIODe
8:31
—
7-42
Individual bits to enable each Interrupt GPIO pin (pins are scattered).
bit 0 controls GPIO_SINT_7 (ETH_16 pin)
bit 1 controls GPIO_SINT_6 (ETH_15 pin)
bit 2 controls GPIO_SINT_5 (ETH_14 pin)
bit 3 controls GPIO_SINT_4 (ETH_13 pin)
bit 4 controls GPIO_SINT_3 (USB1_9 pin)
bit 5 controls GPIO_SINT_2 (PSC3_8 pin)
bit 6 controls GPIO_SINT_1 (PSC3_5 pin)
bit 7 controls GPIO_SINT_0 (PSC3_4 pin)
0 = disabled for GPIO use (default)
1 = enabled for GPIO use
Reserved
2
3
4
5
6
SIODe
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
Individual bits to cause open drain emulation for pins configured as GPIO output.
bit 0 controls GPIO_SINT_7 (ETH_16 pin)
bit 1 controls GPIO_SINT_6 (ETH_15 pin)
bit 2 controls GPIO_SINT_5 (ETH_14 pin)
bit 3 controls GPIO_SINT_4 (ETH_13 pin)
bit 4 controls GPIO_SINT_3 (USB1_9 pin)
bit 5 controls GPIO_SINT_2 (PSC3_8 pin)
bit 6 controls GPIO_SINT_1 (PSC3_5 pin)
bit 7 controls GPIO_SINT_0 (PSC3_4 pin)
0 = Normal CMOS output (default)
1 = Open Drain emulation (a drive to high creates Hi-Z)
Reserved
MPC5200B Users Guide, Rev. 1
Description
7
8
9
10
11
0
0
0
0
23
24
25
26
27
Reserved
0
0
0
0
Description
12
13
14
15
Reserved
0
0
0
0
0
28
29
30
31 lsb
0
0
0
0
0
Freescale Semiconductor
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