Page 1 Freescale Semiconductor MPC850 Family User’s Manual Integrated Communications Microprocessor Supports MPC850 MPC850DE MPC850SR MPC850DSL MPC850UM/D Rev. 1, 1/2001 © Freescale Semiconductor, Inc., 2004. All rights reserved.
Page 2 0120 191014 or +81 3 5437 9125 surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product support.japan@freescale.com could create a situation where personal injury or death may occur. Should Buyer...
Page 3 Part I—Overview MPC850 Overview Memory Map Part II—PowerPC Microprocessor Module PowerPC Core PowerPC Core Register Set MPC850 Instruction Set Exceptions Instruction and Data Caches Memory Management Unit Instruction Execution Timing Part III—PowerPC Microprocessor Module System Interface Unit Reset Part IV—Hardware Interface...
Page 4 Part I—Overview MPC850 Overview Memory Map Part II—PowerPC Microprocessor Module PowerPC Core PowerPC Core Register Set MPC850 Instruction Set Exceptions Instruction and Data Caches Memory Management Unit Instruction Execution Timing Part III—PowerPC Microprocessor Module System Interface Unit Reset Part IV—Hardware Interface...
Page 5 ATM Pace Control ATM Exceptions Interface Conﬁguration UTOPIA Interface Part VII—System Debugging and Testing Support System Development and Debugging IEEE 1149.1 Test Access Port Byte Ordering Serial Communication Performance Register Quick Reference Guide Instruction Set Listings MPC850 MPC850DSL Glossary Index...
Page 6 ATM Pace Controller ATM Exceptions Interface Conﬁguration UTOPIA Interface Part VII—System Debugging and Testing Support System Development and Debugging IEEE 1149.1 Test Access Port Byte Ordering Serial Communication Performance Register Quick Reference Guide Instruction Set Listings MPC850 MPC850DSL Glossary Index...
Page 7: Table Of Contents
1.2.3.3 Memory Controller ................... 1–14 1.2.4 Communications Processor Module (CPM) ..........1–15 1.2.5 System Debugging and Testing Support ............1–17 Differences between the MPC850 Family and MPC860........1–17 Chapter 2 Memory Map Part II PowerPC Microprocessor Module Chapter 3 The PowerPC Core The MPC850 Core as a PowerPC Implementation..........
Page 8 Nonspeculative Load Instructions ............3-13 3.6.3.5 Unaligned Accesses .................. 3-13 3.6.3.6 Atomic Update Primitives ................ 3-14 The MPC850 and the PowerPC Architecture ........... 3-14 Chapter 4 PowerPC Core Register Set MPC850 Register Implementation ..............4-1 4.1.1 PowerPC Registers—User Registers .............. 4-2 4.1.1.1...
Page 9 CONTENTS Paragraph Page Title Number Number 5.2.1.4 Reserved Instruction Class ................. 5-5 5.2.2 Addressing Modes ..................5-5 5.2.2.1 Memory Addressing ................... 5-5 5.2.2.2 Effective Address Calculation ..............5-6 5.2.2.3 Synchronization ..................5-6 5.2.2.3.1 Context Synchronization ................ 5-6 5.2.2.3.2 Execution Synchronization..............5-7 5.2.2.3.3 Instruction-Related Exceptions...............
Page 10 Reading Data and Tags in the Instruction Cache........7–8 7.3.1.2 IC_CST Commands..................7–9 7.3.1.2.1 Instruction Cache Enable/Disable Commands ........7–9 7.3.1.2.2 Instruction Cache Load & Lock Cache Block Command ...... 7–9 7.3.1.2.3 Instruction Cache Unlock Cache Block Command ......7–10 MPC850 Family User’s Manual...
Page 11 CONTENTS Paragraph Page Title Number Number 7.3.1.2.4 Instruction Cache Unlock All Command ..........7–11 7.3.1.2.5 Instruction Cache Invalidate All Command ......... 7–11 7.3.2 Data Cache Control Registers............... 7–11 7.3.2.1 Reading Data Cache Tags and Copyback Buffer ........7–14 7.3.2.2 DC_CST Commands ................7–15 7.3.2.2.1 Data Cache Enable/Disable Commands ..........
Page 12 Memory Management Unit Exceptions ............8–31 8.10 TLB Manipulation .................... 8–31 8.10.1 TLB Reload....................8–32 8.10.1.1 Translation Reload Examples ..............8–32 8.10.2 Locking TLB Entries ..................8–33 8.10.3 Loading Locked TLB Entries ............... 8–34 8.10.4 TLB Invalidation................... 8–34 MPC850 Family User’s Manual...
Page 13 CONTENTS Paragraph Page Title Number Number Chapter 9 Instruction Execution Timing Instruction Execution Timing Examples ............9–1 9.1.1 Data Cache Load with a Data Dependency ............ 9–1 9.1.2 Writeback Arbitration ..................9–2 9.1.3 Private Writeback Bus Load ................9–3 9.1.4 Fastest External Load (Data Cache Miss)............
Page 14 External Soft Reset ..................11–4 11.1.8 Internal Soft Reset ..................11–4 11.1.9 Soft Reset Sequence..................11–5 11.2 Reset Status Register (RSR) ................11–5 11.3 MPC850 Reset Configuration................11–6 11.3.1 Hard Reset..................... 11–7 11.3.1.1 Hard Reset Configuration Word ............... 11–9 11.3.2 Soft Reset....................11–11 11.4 TRST and Power Mode Considerations ............
Page 15 CONTENTS Paragraph Page Title Number Number Part IV The Hardware Interface Chapter 12 External Signals 12.1 System Bus Signals................... 12–5 12.2 Active Pull-Up Buffers ................... 12–18 12.3 Internal Pull-Up and Pull-Down Resistors ............ 12–19 12.4 Recommended Basic Pin Connections ............12–20 12.4.1 Reset Configuration ..................
Page 16 14.3.3 The Time Base and Decrementer Clock (TMBCLK)......... 14–16 14.4 Power Distribution ..................14–16 14.4.1 I/O Buffer Power (VDDH) ................. 14–17 14.4.2 Internal Logic Power (VDDL)..............14–18 14.4.3 Clock Synthesizer Power (VDDSYN, VSSSYN, VSSYN1) ..... 14–18 MPC850 Family User’s Manual...
Page 17 CONTENTS Paragraph Page Title Number Number 14.4.4 Keep-Alive Power (KAPWR) ..............14–18 14.5 Power Control (Low-Power Modes)............... 14–18 14.5.1 Normal High Mode..................14–21 14.5.2 Normal Low Mode..................14–21 14.5.3 Doze High Mode..................14–21 14.5.4 Doze Low Mode ..................14–22 14.5.5 Sleep Mode ....................
Page 18 Synchronous External Masters ..............15–54 15.8.2 Asynchronous External Masters ..............15–55 15.8.3 Special Case: Address Type Signals for External Masters......15–55 15.8.4 UPM Features Supporting External Masters ..........15–55 15.8.4.1 Address Incrementing for External Synchronous Bursting Masters ..15–55 MPC850 Family User’s Manual...
Page 19 CONTENTS Paragraph Page Title Number Number 15.8.4.2 Handshake Mechanism for Asynchronous External Masters ....15–56 15.8.4.3 Special Signal for External Address Multiplexer Control ...... 15–56 15.8.5 External Master Examples ................15–56 15.8.5.1 External Masters and the GPCM ............15–56 15.8.5.2 External Masters and the UPM...............
Page 20 CP Command Register (CPCR)..............18–6 18.5.4 CP Commands ....................18–7 18.5.4.1 CP Command Examples ................18–9 18.5.4.2 CP Command Execution Latency............. 18–9 18.6 Dual-Port RAM....................18–9 18.6.1 System RAM and Microcode Packages............18–11 18.6.2 The Buffer Descriptor (BD)................ 18–12 MPC850 Family User’s Manual...
Page 21 CONTENTS Paragraph Page Title Number Number 18.6.3 Parameter RAM ..................18–12 18.7 The RISC Timer Table..................18–13 18.7.1 RISC Timer Table Scan Algorithm ............18–14 18.7.2 The set timer Command................18–14 18.7.3 RISC Timer Table Parameter RAM and Timer Table Entries ....18–14 18.7.3.1 RISC Timer Command Register (TM_CMD) ........
Page 22 20.2.6 GCI Bus Implementation ................20–28 20.2.6.1 GCI Activation/Deactivation ..............20–30 20.2.6.2 Programming the GCI Interface ............. 20–30 20.2.6.2.1 Normal Mode..................20–30 20.2.6.2.2 SCIT Mode ..................20–30 20.2.6.3 GCI Interface (SCIT Mode) Programming Example ......20–31 MPC850 Family User’s Manual...
Page 23 CONTENTS Paragraph Page Title Number Number 20.3 NMSI Configuration ..................20–32 20.4 Baud Rate Generators (BRGs)................ 20–34 20.4.1 Baud Rate Generator Configuration Registers (BRGCn)......20–36 20.4.2 Autobaud Operation on the SCC UART ............ 20–37 20.4.3 UART Baud Rate Examples ............... 20–38 Chapter 21 Serial Communications Controllers 21.1...
Page 24 HDLC Bus Mode with Collision Detection............ 23–16 23.14.1 HDLC Bus Features..................23–19 23.14.2 Accessing the HDLC Bus ................23–19 23.14.3 Increasing Performance ................23–20 23.14.4 Delayed RTS Mode ..................23–20 23.14.5 Using the Time-Slot Assigner (TSA) ............23–22 MPC850 Family User’s Manual...
Page 25 CONTENTS Paragraph Page Title Number Number 23.14.6 HDLC Bus Protocol Programming............. 23–22 23.14.6.1 Programming GSMR and PSMR for the HDLC Bus Protocol ....23–22 23.14.6.2 HDLC Bus Controller Programming Example........23–23 Chapter 24 SCC AppleTalk Mode 24.1 Operating the LocalTalk Bus ................24–1 24.2 Features ......................
Page 26 SCC Ethernet Mode 27.1 Ethernet on the MPC850................... 27–2 27.2 Features ......................27–3 27.3 Learning Ethernet on the MPC850 ..............27–4 27.4 Connecting the MPC850 to Ethernet ..............27–4 27.5 SCC Ethernet Channel Frame Transmission ............ 27–6 27.6 SCC Ethernet Channel Frame Reception............27–6 27.7...
Page 27 CONTENTS Paragraph Page Title Number Number 27.19 SCC Ethernet Transmit Buffer Descriptor............27–18 27.20 SCC Ethernet Event Register (SCCE)/Mask Register (SCCM) ..... 27–20 27.21 SCC Ethernet Programming Example ............27–21 Chapter 28 SCC Transparent Mode 28.1 Features ......................28–1 28.2 SCC Transparent Channel Frame Transmission Process........
Page 28 30.4.1 SMC Transparent Mode Features ............... 30–21 30.4.2 SMC Transparent-Specific Parameter RAM ..........30–21 30.4.3 SMC Transparent Channel Transmission Process........30–21 30.4.4 SMC Transparent Channel Reception Process ........... 30–22 30.4.5 Using SMSYN for Synchronization ............30–22 MPC850 Family User’s Manual...
Page 29 CONTENTS Paragraph Page Title Number Number 30.4.6 Using TSA for Synchronization ..............30–23 30.4.7 SMC Transparent Commands..............30–25 30.4.8 Handling Errors in the SMC Transparent Controller........30–26 30.4.9 SMC Transparent Receive BD (RxBD)............30–26 30.4.10 SMC Transparent Transmit BD (TxBD) ............ 30–27 30.4.11 SMC Transparent Event Register (SMCE)/Mask Register (SMCM)..
Page 30 I2C Controller Clocking and Signal Functions..........33–2 33.3 I2C Controller Transfers ................... 33–3 33.3.1 C Master Write (Slave Read)..............33–3 33.3.2 C Loopback Testing................... 33–4 33.3.3 C Master Read (Slave Write)..............33–4 33.3.4 C Multi-Master Considerations ..............33–5 MPC850 Family User’s Manual...
Page 31 CONTENTS Paragraph Page Title Number Number 33.4 I2C Registers..................... 33–6 33.4.1 C Mode Register (I2MOD)................ 33–6 33.4.2 C Address Register (I2ADD)..............33–7 33.4.3 C Baud Rate Generator Register (I2BRG)..........33–7 33.4.4 C Event/Mask Registers (I2CER/I2CMR)..........33–8 33.4.5 C Command Register (I2COM)..............33–8 33.5 I2C Parameter RAM ..................
Page 32 Interrupt Handler Example—Multiple-Event Interrupt Source...... 35–11 Part VI Asynchronous Transfer Mode (ATM) Chapter 36 ATM Overview 36.1 ATM Capabilities....................36–1 36.2 MPC850SR and MPC850 Differences ............. 36–1 36.2.1 Parameter RAM Conflicts ................36–1 36.2.2 IDMA2 Restriction ..................36–2 36.2.3 UTOPIA Conflicts ..................36–2 36.2.4 The ATM Pace Controller (APC) and APC Timer........
Page 33 CONTENTS Paragraph Page Title Number Number 36.7.3 Cell Payload Scrambling/Descrambling............36–9 36.8 ATM Pace Control (APC) ................36–10 36.9 Internal and External Channels (Extended Channel Mode) ......36–10 Chapter 37 Buffer Descriptors and Connection Tables 37.1 ATM Buffer Descriptors (BDs) ................ 37–1 37.1.1 AAL5 Buffers ....................
Page 34 Chapter 41 ATM Exceptions 41.1 ATM Event Registers ..................41–2 41.1.1 UTOPIA Event Register (IDSR1) ..............41–2 41.1.2 Serial ATM Event Register (SCCE)............. 41–3 41.2 Interrupt Queue Entry ..................41–4 41.3 Interrupt Queue Mask (IMASK)............... 41–6 MPC850 Family User’s Manual...
Page 35 CONTENTS Paragraph Page Title Number Number Chapter 42 Interface Configuration 42.1 General ATM Registers ..................42–1 42.1.1 Port D Pin Assignment Register (PDPAR)........... 42–1 42.1.2 APC Timer (CPM Timer 4) ................42–2 42.1.3 RISC Timer....................42–2 42.2 UTOPIA Mode Registers.................. 42–2 42.2.1 System Clock Control Register (SCCR)............
Page 36 Generating Six Compare Types.............. 44–18 44.2.5 Load/Store Breakpoint Example..............44–18 44.3 Development System Interface ............... 44–19 44.3.1 Debug Mode Operation ................44–21 44.3.1.1 Debug Mode Enable vs. Debug Mode Disable ........44–22 44.3.1.2 Entering Debug Mode................44–23 MPC850 Family User’s Manual...
Page 37 CONTENTS Paragraph Page Title Number Number 44.3.1.3 Debug Mode Indication ................44–24 44.3.1.4 Checkstop State and Debug Mode............44–24 44.3.1.5 Saving Machine State when Entering Debug Mode....... 44–25 44.3.1.6 Running in Debug Mode ................ 44–25 44.3.1.7 Exiting Debug Mode................44–25 44.3.2 Development Port Communication ............
Page 38 45.4.5 HI–Z......................45–7 45.5 TAP Usage Considerations ................45–8 45.6 Recommended TAP Configuration..............45–8 45.7 Motorola MPC850 BSDL Description ............. 45–8 Appendix A Byte Ordering Byte Ordering Overview..................A-1 MPC850 Byte-Ordering Mechanisms..............A-1 BE Mode ......................A-2 TLE Mode......................A-2 A.4.1...
Page 39 Number Appendix C Register Quick Reference Guide PowerPC Registers—User Registers ..............C-1 PowerPC Registers—Supervisor Registers ............C-2 MPC850-Specific SPRs ..................C-3 Appendix D Instruction Set Listings Instructions Sorted by Mnemonic..............D-1 Instructions Sorted by Opcode................D-9 Instructions Grouped by Functional Categories ..........D-17 Instructions Sorted by Form................
Page 40 CONTENTS Paragraph Page Title Number Number MPC850 Family User’s Manual...
Page 41 Page Title Number Number MPC850SR Family Microprocessor Block Diagram ...........1–3 MPC850 Functional Signal Diagram................1–12 Block Diagram of the Core ................... 3-4 Instruction Flow Conceptual Diagram................3-6 Basic Instruction Pipeline Timing ................3-7 Sequencer Data Path ..................... 3-8 LSU Functional Block Diagram ................. 3-11 Condition Register (CR) ....................
Page 42: System Configuration
10-4 System Protection Control Register (SYPCR) ............10–8 10-5 Transfer Error Status Register (TESR) ...............10–9 10-6 Register Lock Mechanism ..................10–11 10-7 MPC850 Interrupt Structure ..................10–12 10-8 SIU Interrupt Processing...................10–14 10-9 IRQ0 Logical Representation ...................10–14 10-10 SIU Interrupt Pending Register (SIPEND) ...............10–15 10-11 SIU Interrupt Mask Register (SIMASK) ..............10–17...
Page 43 Reset Configuration Sampling Timing Requirements..........11–9 11-8 Hard Reset Configuration Word .................11–9 12-1 MPC850 Signals Group ....................12–2 12-2 MPC850 Signals and Pin Numbers (Part 1) ...............12–3 12-3 MPC850 Signals and Pin Numbers (Part 2) ...............12–4 12-4 Three-State Buffers and Active Pull-Up Buffers............12–19 13-1 Input Sample Window ....................13–2...
Page 44 Diagram for (CSRC=0 and DFNH=1) or (CSRC=1 and DFNL=0)......14–13 14-10 BRGCLK Divider .....................14–14 14-11 SYNCCLK Divider....................14–15 14-12 MPC850 Power Rails....................14–17 14-13 MPC850 Low-Power Mode Flowchart..............14–20 14-14 Software-Initiated Power-Down Configuration............14–25 14-15 System Clock and Reset Control Register (SCCR) ..........14–27 14-16 PLL, Low-Power, and Reset Control Register (PLPRCR)........14–30 15-1 Memory Controller Block Diagram ................15–3...
Page 45 ILLUSTRATIONS Figure Page Title Number Number 15-21 GPCM Relaxed Timing Read (ACS = 1x, SCY = 1, CSNT = 0, and TRLX = 1) ..................15–23 15-22 GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 0, TRLX = 1) ..15–24 15-23 GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 1, TRLX =1) ..15–25 15-24...
Page 46 Timer Capture Registers (TCR1–TCR4) ..............17–10 17-9 Timer Counter Registers (TCN1–TCN4) ..............17–11 17-10 Timer Event Registers (TER1–TER4)..............17–11 18-1 Communications Processor (CP) Block Diagram............18–2 18-2 RISC Controller Configuration Register (RCCR) ............18–4 18-3 RISC Microcode Development Support Control Register (RMDS)......18–5 MPC850 Family User’s Manual...
Page 47 RISC Timer Table RAM Usage................18–14 18-8 RISC Timer Command Register (TM_CMD) ............18–15 18-9 RISC Timer Event Register (RTER)/Mask Register (RTMR) .........18–16 19-1 MPC850 SDMA Data Paths ..................19–1 19-2 SDMA U-Bus Arbitration (Cycle Steal)..............19–3 19-3 SDMA Configuration Register (SDCR) ..............19–4 19-4 SDMA Status Register (SDSR) ..................19–4...
Page 48 SCC HDLC Receive Buffer Descriptor (RxBD) ............23–8 23-5 SCC HDLC Receiving using RxBDs ...............23–10 23-6 SCC HDLC Transmit Buffer Descriptor (TxBD).............23–11 23-7 HDLC Event Register (SCCE)/HDLC Mask Register (SCCM) ......23–12 23-8 SCC HDLC Interrupt Event Example...............23–13 MPC850 Family User’s Manual...
Page 49 26-9 SCC Status Registers (SCCS)...................26–16 27-1 Ethernet Frame Structure ....................27–1 27-2 Ethernet Block Diagram .....................27–2 27-3 Connecting the MPC850 to Ethernet ................27–5 27-4 Ethernet Address Recognition Flowchart ..............27–12 27-5 Ethernet Mode Register (PSMR) ................27–15 27-6 SCC Ethernet RxBD ....................27–16 27-7 Ethernet Receiving using RxBDs ................27–18...
Page 50 SPI Transfer Format with SPMODE[CP] = 0 ............31–8 31-6 SPI Transfer Format with SPMODE[CP] = 1 ............31–8 31-7 SPI Event/Mask Registers (SPIE/SPIM) ..............31–10 31-8 SPI Command Register (SPCOM)................31–10 31-9 Receive/Transmit Function Code Registers (RFCR/TFCR)........31–12 31-10 SPI Memory Structure ....................31–13 MPC850 Family User’s Manual...
Page 51 ILLUSTRATIONS Figure Page Title Number Number 31-11 SPI Receive BD (RxBD) ..................31–14 31-12 SPI Transmit BD (TxBD) ..................31–15 32-1 USB Controller Block Diagram..................32–2 32-2 USB Interface......................32–4 32-3 USB Controller Operation Flow .................32–5 32-4 Endpoint Pointer Registers (EPnPTR)................32–8 32-5 Frame Number (FRAME_N)..................32–9 32-6 Transmit/Receive Function Code Registers (TFCR/RFCR)........32–9 32-7...
Page 52 Port D Data Register (PDDAT) ................34–17 34-17 Port D Data Direction Register (PDDIR) ..............34–18 34-18 Port D Pin Assignment Register (PDPAR)...............34–18 35-1 MPC850 Interrupt Structure ..................35–2 35-2 Interrupt Request Masking..................35–5 35-3 CPM Interrupt Configuration Register (CICR) ............35–7 35-4 CPM Interrupt Pending/Mask/In-Service Registers (CIPR/CIMR/CISR) ....35–8 35-5 CPM Interrupt Vector Register (CIVR)..............35–10...
Page 53 Instruction Support General Structure ..............44–12 44-3 Load/Store Support General Structure..............44–13 44-4 Partially Supported Watchpoints/Breakpoint Example ..........44–17 44-5 Functional Diagram of the MPC850 Debug Mode Support ........44–20 44-6 Debug Mode Logic Diagram ..................44–21 44-7 Debug Mode Reset Configuration Timing Diagram ..........44–22 44-8 Development Port/BDM Connector Pinout Options ..........44–27...
Page 54 ILLUSTRATIONS Figure Page Title Number Number 45-7 Bypass Register......................45–7 TLE Mode Mechanisms....................A-3 Byte Swapping ......................A-4 PPC-LE Mode Mechanisms..................A-7 MPC850 Block Diagram....................E–2 MPC850DSL Block Diagram ..................F–2 MPC850 Family User’s Manual...
Page 55 Table Page Title Number Number MPC850 Functionality Matrix..................1–2 MPC850 Internal Memory Map..................2-1 Static Branch Prediction ....................3-9 Bus Cycles Needed for Single-Register Load/Store Accesses ........3-13 UISA-Level Features ....................3-15 VEA-Level Features ....................3-16 OEA-Level Features ....................3-17 User-Level PowerPC Registers..................4-2 User-Level PowerPC SPRs...................
Page 56 Identical Entries Required in Level-One/Level-Two Tables........8–10 Number of Replaced EA Bits per Page Size...............8–11 Level-One Segment Descriptor Format ..............8–12 Level-Two (Page) Descriptor Format.................8–13 Page Size Selection .....................8–14 MPC850-Specific MMU SPRs ...................8–14 MI_CTR Field Descriptions ..................8–16 MD_CTR Field Descriptions..................8–17 Mx_EPN Field Descriptions ..................8–18 8-10 MI_TWC Field Descriptions ..................8–18...
Page 57 RTSEC Field Descriptions..................10–31 10-24 PISCR Field Descriptions ..................10–32 10-25 PITC Field Descriptions ...................10–33 10-26 PITR Field Descriptions ...................10–34 11-1 MPC850 Reset Responses ..................11–1 11-2 Reset Status Register Bit Settings................11–6 11-3 Hard Reset Configuration Word Field Descriptions...........11–9 12-1 Signal Descriptions .....................12–5 12-2 Active Pull-Up Resistors Enabled as Outputs ............12–19...
Page 58 XFC Capacitor Values Based on PLPRCR[MF] ............14–8 14-3 Functionality Summary of the Clocks ................14–9 14-4 PITRTCLK Configuration at PORESET..............14–16 14-5 TMBCLK Configuration ..................14–16 14-6 MPC850 Modules vs. Power Rails ................14–17 14-7 MPC850 Low-Power Modes ..................14–19 14-8 SCCR Field Descriptions..................14–28 14-9 PLPRCR Field Descriptions ..................14–30 14-10 PLPRCR[CSR] and DER[CHSTPE] Bit Combinations...........14–31...
Page 59 TABLES Table Page Title Number Number 16-8 PIPR Field Descriptions....................16–9 16-9 PSCR Field Descriptions ....................16–9 16-10 PER Field Descriptions.....................16–10 16-11 PGCRB Field Descriptions ..................16–12 16-12 PBR Field Descriptions.....................16–12 16-13 POR Field Descriptions ....................16–13 17-1 TGCR Field Descriptions ...................17–8 17-2 TMR1–TMR4 Field Descriptions................17–9 17-3 TER Field Descriptions.....................17–11 18-1...
Page 60 Asynchronous HDLC-Specific SCC Parameter RAM Memory Map ......25–5 25-2 Asynchronous HDLC-Specific GSMR Field Descriptions ........25–7 25-3 Transmit Commands....................25–8 25-4 Receive Commands ....................25–8 25-5 Transmit Errors ......................25–8 25-6 Receive Errors......................25–9 25-7 SCCE/SCCM Field Descriptions................25–10 25-8 Asynchronous HDLC SCCS Field Descriptions ............25–11 MPC850 Family User’s Manual...
Page 61 TABLES Table Page Title Number Number 25-9 PSMR Field Descriptions ..................25–11 25-10 Asynchronous HDLC RxBD Status and Control Field Descriptions .......25–12 25-11 Asynchronous HDLC TxBD Status and Control Field Descriptions .......25–13 26-1 SCC BISYNC Parameter RAM Memory Map............26–4 26-2 Transmit Commands....................26–5 26-3 Receive Commands ....................26–5 26-4...
Page 62 USADR Field Descriptions..................32–11 32-9 USEPn Field Descriptions ..................32–12 32-10 USCOM Field Descriptions..................32–13 32-11 USBER/USBMR Field Descriptions ................32–13 32-12 USBS Field Descriptions ..................32–14 32-13 RxBD Status and Control Field Descriptions ............32–17 32-14 TxBD Status and Control Field Descriptions ............32–19 MPC850 Family User’s Manual...
Page 63 TABLES Table Page Title Number Number 32-15 USB Command Format Field Descriptions ..............32–20 32-16 USB Controller Transmission Errors................32–21 32-17 USB Controller Reception Errors ................32–22 33-1 I2MOD Field Descriptions ..................33–6 33-2 I2ADD Field Descriptions ..................33–7 33-3 I2BRG Field Descriptions...................33–8 33-4 I2CER/I2CMR Field Descriptions................33–8 33-5 I2COM Field Descriptions..................33–9 33-6...
Page 64 Debug Port Command Shifted Into Development Port Shift Register .....44–31 44-12 Status/Data Shifted Out of Development Port Shift Register........44–32 44-13 Debug Instructions/Data Shifted Into Development Port Shift Register ....44–33 44-14 MPC850-Specific Development Support and Debug SPRs ........44–36 44-15 Development Support/Debug Registers Protection ..........44–37 44-16 CMPA–CMPD Field Descriptions ................44–37 44-17 CMPE–CMPF Field Descriptions................44–38...
Page 65 Little-Endian Program/Data Path Between the Register and 16-Bit Memory..... A-5 Little-Endian Program/Data Path between the Register and 8-Bit Memory ....A-6 PPC-LE 3-bit Munging ....................A-7 MPC850 Serial Performance at 25 MHz ..............B-4 IDMA Performance at 25 MHz ..................B-5 User-Level PowerPC Registers..................C-1 User-Level PowerPC SPRs...................C-1...
Page 66 XL-Form ........................D-34 D-38 XFX-Form........................D-35 D-39 XFL-Form ........................D-35 D-40 XS-Form ........................D-35 D-41 XO-Form........................D-35 D-42 A-Form........................D-36 D-43 M-Form ........................D-37 D-44 MD-Form ........................D-37 D-45 MDS-Form......................... D-39 D-46 Instruction Set Legend ....................D-41 MPC850 Family User’s Manual...
Page 67: About This Book
To locate any published errata or updates for this document, refer to the world-wide web at http://www.motorola.com/SPS/RISC/netcomm.. Note that this manual supports all members of the MPC850 family, however it is written from the perspective of the MPC850DE, which is the superset of the basic MPC850 device.
Page 68 Audience This manual is intended for software and hardware developers and application programmers who want to develop products for the MPC850. It is assumed that the reader has a basic understanding of computer networking, OSI layers, and RISC architecture. In addition, it is assumed that the reader has a basic understanding of the communications protocols described here.
Page 69: Serial Interface
— Chapter 11, “Reset,” describes the behavior of the MPC850 at reset and start-up. • Part IV, “The Hardware Interface,” describes external signals, clocking, memory control, and power management of the MPC850.
Page 70: Scc Uart Mode
— Chapter 32, “Universal Serial Bus Controller,” describes the MPC850 implementation of the universal serial bus, an industry-standard extension to the PC architecture that supports data exchange between the MPC850 and a PC host and a wide range of simultaneously accessible peripherals.
Page 71 MPC850DSL ATM implementation. It consists of the following chapters: — Chapter 36, “ATM Overview,” gives a high-level description of the MPC850SR and MPC850 DSL ATM implementation, which includes support for aUTOPIA level 1 interface. — Chapter 37, “Buffer Descriptors and Connection Tables,” describes the structure and conﬁguration of the buffer descriptors (BDs) and the transmit and receive...
Page 72 (TAP), which is fully compatible with the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. • Appendix A, “Byte Ordering,” discusses the MPC850 implementation of little- and big-endian byte mapping. • Appendix B, “Serial Communications Performance,”provides guidelines for maximizing performance of MPC850-based systems.
Page 73 • Programming environments manuals—These books provide information about resources deﬁned by the PowerPC architecture that are common to PowerPC processors. There are two versions, one that describes the functionality of the combined 32- and 64-bit architecture models and one that describes only the 32-bit model.
Page 74: Acronyms And Abbreviations
Bus unit ID Content-addressable memory CEPT Conference des administrations Europeanes des Postes et Telecommunications (European Conference of Postal and Telecommunications Administrations). Communications processor Communications processor module Condition register Cyclic redundancy check Count register DABR Data address breakpoint register MPC850 Family User’s Manual...
Page 75 Table i. Acronyms and Abbreviated Terms (Continued) Term Meaning Data address register Decrementer register Direct memory access DPLL Digital phase-locked loop DRAM Dynamic random access memory DSISR Register used for determining the source of a DSI exception DTLB Data translation lookaside buffer Effective address EEST Enhanced Ethernet serial transceiver...
Page 76 Read with intent to modify Receive Serial communications controller Serial control port SDLC Synchronous Data Link Control SDMA Serial DMA Serial interface SIMM Signed immediate value System interface unit Serial management controller Systems network architecture Serial peripheral interface Special-purpose register MPC850 Family User’s Manual...
Page 77 Table i. Acronyms and Abbreviated Terms (Continued) Term Meaning SPRGn Registers available for general purposes SRAM Static random access memory SRR0 Machine status save/restore register 0 SRR1 Machine status save/restore register 1 Test access port Time base register Time-division multiplexed Translation lookaside buffer Time-slot assigner Transmit...
Page 78 Table iii. Instruction Field Conventions The Architecture Speciﬁcation Equivalent to: crbA, crbB, crbD (respectively) BA, BB, BT BF, BFA crfD, crfS (respectively) rA, rB, rD, rS (respectively) RA, RB, RT, RS SIMM UIMM /, //, /// 0...0 (shaded) MPC850 Family User’s Manual...
Page 79: Intended Audience
Part I is intended for anyone who needs a high-level understanding of the MPC850 Family of PowerQuicc devices. Contents Part I provides an overview of the features and functions of the MPC850. It includes the following chapters: • Chapter 1, “Overview, ” provides a high-level description of MPC850 Family functions and features.
Page 80 Institute of Electrical and Electronics Engineers IrDA Infrared Data Association ISDN Integrated services digital network ITLB Instruction translation lookaside buffer Integer unit JTAG Joint Test Action Group Least recently used (cache replacement algorithm) Load/store unit Memory management unit MPC850 Family User’s Manual...
Page 81 Table i. Acronyms and Abbreviated Terms (Continued) Term Meaning Machine state register NMSI Nonmultiplexed serial interface Operating environment architecture Open systems interconnection Peripheral component interconnect PCMCIA Personal Computer Memory Card International Association RISC Reduced instruction set computing RTOS Real-time operating system Receive Serial communications controller SDLC...
Page 82 MPC850 Family User’s Manual...
Page 83 (referred to as the CP). This separate processor off-loads peripheral tasks from the embedded PowerPC core. The CPM of the MPC850 supports up to seven serial channels, as follows: • One or two serial communications controllers (SCCs). The SCCs support Ethernet, ATM (MPC850SR and MPC850DSL), HDLC and a number of other protocols, along with a transparent mode of operation.
Page 84: Features
SMC2 and I C are not supported. interface Appendix G 1.1 Features Figure 1-1 is the block diagram of the MPC850SR, the superset of the MPC850 family, showing the major components and the relationships among those components: MPC850 Family User’s Manual...
Page 85 Time Slot Assigner Non-Multiplexed Serial Interface Figure 1-1. MPC850SR Family Microprocessor Block Diagram The following list summarizes the main features of the MPC850 Family: • Embedded PowerPC core — Single-issue, 32-bit version of the embedded PowerPC core (fully compatible with PowerPC user instruction set architecture deﬁnition) with 32 x 32-bit integer registers —...
Page 86 — Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory) — Variable block sizes, 32 Kbyte to 256 Mbyte — Selectable write protection — On-chip bus arbitration supports external bus master — Special features for burst mode support MPC850 Family User’s Manual...
Page 87 Features • General-purpose timers — Four 16-bit timers or two 32-bit timers — Gate mode can enable/disable counting — Interrupt can be masked on reference match and event capture • Interrupts — Eight external interrupt request (IRQ) lines — Twelve port pins with interrupt capability —...
Page 88 CPM in low-power standby — Sleep: all units disabled except real-time clock and periodic interrupt timer. PLL is active for fast wake-up — Deep sleep: all units disabled including PLL, except the real-time clock and periodic interrupt timer MPC850 Family User’s Manual...
Page 89: Overview Of Major Components
— Eight comparators: four operate on instruction address, two operate on data address, and two operate on data — The MPC850 can compare using the =, ≠, <, and > conditions to generate watchpoints — Each watchpoint can generate a breakpoint internally •...
Page 90: Powerpc Microprocessor Module
1.2.2 Conﬁguration and Reset The MPC850 conﬁguration is handled through the system interface unit (SIU), which is described in Section 1.2.2.1, “System Interface Unit (SIU).” The MPC850 provides many different kinds of reset, as described in Section 1.2.2.2, “Resets.”...
Page 91: Resets
256 Mbytes for 32-bit memory. The DRAM controller supports page mode access for successive transfers within bursts. The MPC850 supports a glueless interface to one bank of DRAM, while external buffers are required for additional memory banks. The refresh...
Page 92: Mpc850 Hardware Interface
1.2.3 MPC850 Hardware Interface The MPC850 bus is a synchronous, burstable bus that can support multiple masters. Signals driven on this bus are required to make the setup and hold time relative to the bus clock’s rising edge. The MPC850 architecture supports byte, half-word, and word operands allowing access to 8-, 16-, and 32-bit data ports through the use of synchronous cycles controlled by the size outputs (TSIZ0, TSIZ1).
Page 93: Signals
Overview of Major Components 1.2.3.1 Signals Figure 1-2 shows MPC850 signals grouped by function. Note that many of these signals are multiplexed and this ﬁgure does not indicate how these signals are multiplexed. For signals available on the MPC850SR and MPC850DSL, refer to Part VI ATM.
Page 94 TIN[1–4] → 4 1 ← VBSSSYN TGATE1 → 1 1 ← VSSSYN1 MODCK[1–2] → 2 1 ← KAPWR Power SPKROUT ← 1 1 ← VDDH 1 ← VDDL 1 ← VSS Figure 1-2. MPC850 Functional Signal Diagram MPC850 Family User’s Manual...
Page 95: Clocking And Power Management
These modes progressively reduce power consumption, as follows: • In full-high mode, the MPC850 is fully powered with all internal units operating at the full processor speed. • Full-low mode is the same as full-high, but operates at a lower frequency. A gear mode determined by a clock divider allows the operating system to reduce the operational frequency of the processor.
Page 96: Memory Controller
• General-purpose chip-select machine (GPCM) — Compatible with SRAM, EPROM, FEPROM, and peripherals — Global (boot) chip-select available at system reset — Boot chip-select support for 8-, 16-, and 32-bit devices — Minimum two clock accesses to external device MPC850 Family User’s Manual...
Page 97: Communications Processor Module (Cpm)
Overview of Major Components — Four byte write enable signals (WE) — Output enable signal (OE) • Two user-programmable machines (UPMs) — Programmable-array-based machine controls external signal timing with a granularity of one quarter of an external bus clock period —...
Page 98 • By supporting multibuffer memory data structures that are convenient for software handling. The CPMs are similar in the MPC850 and MPC860; both are derived from the CPM in the MC68360 QUICC; see the MC68360 Quad Integrated Communications Controller (QUICC) User’s Manual.
Page 99: System Debugging And Testing Support
The MPC850 can compare using the =, ≠, <, and > conditions to generate watchpoints. Each watchpoint can then generate a breakpoint that can be programmed to trigger on a programmable number of events.
Page 100 Differences between the MPC850 Family and MPC860 • Smaller caches (2-Kbyte instruction cache and 1-Kbyte data cache) • Smaller MMUs (eight entries instead of 32) • Only one PCMCIA slot is supported • Only one TDM port is supported (TDMa) •...
Page 101: Memory Map
Chapter 2 Memory Map Each memory resource in the MPC850 is mapped within a contiguous block of 16 Kbyte memory. The location of this block within the global 4-Gbyte physical memory space can be mapped on 64-Kbyte resolution through an implementation-speciﬁc special-purpose register (SPR) called the internal memory map register (IMMR).
Page 102 Table 2-1. MPC850 Internal Memory Map (Continued) Offset Name Size Section/Page PBR4—PCMCIA interface base register 4 32 bits 16.4.5/-12 POR4—PCMCIA interface option register 4 32 bits 16.4.6/-12 PBR5—PCMCIA interface base register 5 32 bits 16.4.5/-12 POR5—PCMCIA interface option register 5 32 bits 16.4.6/-12...
Page 103 Table 2-1. MPC850 Internal Memory Map (Continued) Offset Name Size Section/Page MAR—Memory address register 32 bits 15.4.7/-17 MCR—Memory command register 32 bits 15.4.5/-15 16C–16F Reserved 4 bytes — MAMR—Machine A mode register 32 bits 15.4.4/-13 MBMR—Machine B mode register 32 bits 15.4.4/-13...
Page 104 Table 2-1. MPC850 Internal Memory Map (Continued) Offset Name Size Section/Page TBREFAK—Timebase reference register A key 32 bits 10.4.5/-10 TBREFBK—Timebase reference register B key 32 bits 10.4.5/-10 TBK—Timebase/decrementer register key 32 bits 10.4.5/-10 310–31F Reserved 16 bytes — RTCSCK—Real-time clock status and control 32 bits 10.4.5/-10...
Page 105 Table 2-1. MPC850 Internal Memory Map (Continued) Offset Name Size Section/Page SDSR—SDMA status register 8 bits 19.2.2/-4 909–90B Reserved 3 bytes — SDMR—SDMA mask register 8 bits 19.2.3/-5 90D–90F Reserved 3 bytes — IDSR1—IDMA1 status register 8 bits 19.3.9.2/-19 911–913...
Page 106 Table 2-1. MPC850 Internal Memory Map (Continued) Offset Name Size Section/Page 978–97F UTMODE—UTOPIA mode register 4 bytes 42.2/-1 978–97F Reserved 8 bytes — CPM General-Purpose Timers TGCR—Timer global conﬁguration register 16 bits 17.2.3.1/-8 982–98F Reserved 14 bytes — TMR1—Timer 1 mode register 16 bits 17.2.4/-9...
Page 107 Table 2-1. MPC850 Internal Memory Map (Continued) Offset Name Size Section/Page RCTR3—RISC controller trap register 3 16 bits Used only by optional RAM microcode RCTR4—RISC controller trap register 4 16 bits Used only by optional RAM microcode 9D4–9D5 Reserved 2 bytes —...
Page 108 Table 2-1. MPC850 Internal Memory Map (Continued) Offset Name Size Section/Page TODR2—SCC2 transmit on demand register 16 bits 21.2.4/-10 DSR2—SCC2 data synchronization register 16 bits 21.2.3/-9 SCCE2—SCC2 event register 16 bits 22.20/-20 (UART) 23.11/-12 (HDLC) 25.13.1/-9 (Asynchronous HDLC) 26.15/-16 (BISYNC) 28.13/-12 (Transparent)
Page 109 Table 2-1. MPC850 Internal Memory Map (Continued) Offset Name Size Section/Page Serial Management Controller 1 (SMC1) SMCMR1—SMC1 mode register 16 bits 30.2.1/-3 A84–A85 Reserved 2 bytes — SMCE1—SMC1 event register 8 bits 30.3.12/-18 (UART) 30.4.11/-29 (Transparent) 30.5.9/-36 (GCI) A87–A89 Reserved 3 bytes —...
Page 110 Table 2-1. MPC850 Internal Memory Map (Continued) Offset Name Size Section/Page SIGMR—SI global mode register 8 bits 20.2.4.1/-14 Reserved 8 bits — SISTR—SI status register 8 bits 20.2.4.5/-22 SICMR—SI command register 8 bits 20.2.4.4/-22 AE8–AEB Reserved 4 bytes — SICR—SI clock route register 32 bits 20.2.4.3/-20...
Page 111 (MMU), cache model, exception model, and an overview of instruction timing. It contains the following chapters: • Chapter 3, “The PowerPC Core,” provides an overview of the MPC850 core, summarizing topics described in further detail in subsequent chapters in Part II.
Page 112 This section lists additional reading that provides background for the information in this manual as well as general information about the PowerPC architecture. MPC8xx Documentation Supporting documentation for the MPC850 can be accessed through the world-wide web at http://www.motorola.com/SPS/RISC/netcomm. This documentation includes technical speciﬁcations, reference materials, and detailed applications notes.
Page 113 • Application notes—These short documents contain useful information about speciﬁc design issues useful to programmers and engineers working with PowerPC processors. Supporting documentation such as technical speciﬁcations, reference materials, and detailed applications notes can be accessed through the world-wide web by using the following URLs: •...
Page 114 Floating-point status and control register General-purpose register IEEE Institute of Electrical and Electronics Engineers ITLB Instruction translation lookaside buffer Integer unit LIFO Last-in-ﬁrst-out Link register Least recently used Least-signiﬁcant byte Least-signiﬁcant bit Load/store unit Memory management unit MPC850 Family User’s Manual...
Page 115 Table i. Acronyms and Abbreviated Terms (Continued) Term Meaning Most-signiﬁcant byte Most-signiﬁcant bit Machine state register Not a number No-op No operation Operating environment architecture Peripheral component interconnect Processor version register RISC Reduced instruction set computing RTOS Real-time operating system RWITM Read with intent to modify Receive...
Page 116 Table iii. Instruction Field Conventions The Architecture Speciﬁcation Equivalent to: crbA, crbB, crbD (respectively) BA, BB, BT crfD, crfS (respectively) BF, BFA rA, rB, rD, rS (respectively) RA, RB, RT, RS SIMM UIMM /, //, /// 0...0 (shaded) MPC850 Family User’s Manual...
Page 117: The Mpc850 Core As A Powerpc Implementation
Programming Environments for 32-Bit Microprocessors, which provides a more in-depth discussion of issues related to the 32-bit portion of the PowerPC architecture. The subset of PowerPC instructions supported by the MPC850 are listed in Chapter 5, “MPC850 Instruction Set.” 3.1 The MPC850 Core as a PowerPC Implementation The core implements all PowerPC user-level instructions deﬁned for 32-bit...
Page 118 • Support for 64-bit addressing. The architecture supports both 32-bit or 64-bit implementations. This document describes the 32-bit portion of the PowerPC architecture. For information about the 64-bit architecture, see PowerPC Microprocessor Family: The Programming Environments. MPC850 Family User’s Manual...
Page 119: Levels Of The Powerpc Architecture
Implementations that conform to the PowerPC OEA also conform to the PowerPC UISA and VEA. The MPC850 adheres to the OEA deﬁnition of the exception model and provides a subset of the memory management model. It includes OEA-deﬁned registers and instructions for conﬁguration and exception handling.
Page 120: Features
Features 3.3 Features Figure 3-1 shows the basic features of the MPC850. 32-Bit (One Instruction) 32-Bit Sequential Completion Branch Fetcher Queue Processing Unit 32-Bit Instruction Queue INSTRUCTION UNIT 32-Bit (One Instruction) One Instruction Retired per Clock 32-Bit 32-Bit Integer GPR File...
Page 121: Basic Structure Of The Core
— Static branch prediction — Precise exception model that includes the subset of the PowerPC exceptions that supports the instruction set and memory management. The MPC850 implements all PowerPC asynchronous exceptions (interrupts)—system reset, machine check, decrementer, and external interrupts. MPC850-speciﬁc exceptions are PowerPC-compliant.
Page 122: Instruction Flow
This information is used to enable out-of-order completion of instructions and ensure a precise exception model. An instruction can be retired after all instructions ahead of it have retired and it updates the architected destination registers without taking an exception. MPC850 Family User’s Manual...
Page 123: Basic Instruction Pipeline
Basic Structure of the Core 3.4.2 Basic Instruction Pipeline Figure 3-3 shows instruction pipeline timing, showing how by distributing the processes required to fetch, execute, and retire an instruction into stages, multiple instructions can be processed during a single clock cycle. Gclk1 addic mulli...
Page 124 PowerPC UISA) determines which instruction stream is prefetched while the branch is being resolved. When the branch operand becomes available, it is forwarded to the BPU and the condition is evaluated. The static branch prediction mechanism is shown in Table 3-1. MPC850 Family User’s Manual...
Page 125: Dispatching Instructions
3.5 Register Set Registers implemented in the MPC850 core can be grouped as follows: • PowerPC registers. The MPC850 implements the user registers deﬁned by the UISA and VEA portions of the architecture except for those that support ﬂoating-point operations. PowerPC registers implemented on the MPC850 are described in Section 4.1.1, “PowerPC Registers—User Registers,”...
Page 126: Branch Processing Unit
• In the cmpi, cmp, cmpli, and cmpl instructions, the L bit is applicable for 64-bit implementations. For the MPC850, if L = 1 the instruction form is invalid. The core ignores this bit and, therefore, the behavior when L = 1 is identical to the valid form instruction with L = 0.
Page 127 Execution Units The following lists the LSU’s main features: • All instructions implemented in hardware, including unaligned, string, and multiple accesses • Two-entry load/store instruction address queue • Pipelined operation. The LSU pipelines load accesses. Individual cache accesses of all multiple-register instructions and unaligned accesses are pipelined into the data cache interface.
Page 128: Executing Load/Store Instructions
ﬁnished without an exception. If a store instruction follows a load instruction, a one-clock delay is inserted between the load bus cycle termination and the store cycle issue. MPC850 Family User’s Manual...
Page 129: Nonspeculative Load Instructions
Execution Units 3.6.3.4 Nonspeculative Load Instructions Load instructions targeted at nonspeculative memory are identiﬁed as nonspeculative one clock cycle after the previous load/store bus cycle ends, only if all prior instructions have ﬁnished without an exception. The nonspeculative identiﬁcation relates to the state of the cycle’s associated instruction. For lmw, although the accesses are pipelined into the bus, they are all marked as nonspeculative because the instruction is nonspeculative.
Page 130: Atomic Update Primitives
• The PowerPC architecture deﬁnes optional features, some of which are implemented on the MPC850 (such as TLBs) and some of which are not, such as the eciwx and ecowx instructions. • The PowerPC architecture deﬁnes features, such as virtual memory and ﬂoating-point instructions, that are not implemented on the MPC850.
Page 131 In the cmpi, cmp, cmpli, and cmpl instructions, the L bit is applicable for 64-bit implementations. For the MPC850, if L = 1 the instruction form is invalid. The core ignores this bit and, therefore, the behavior when L = 1 is identical to the valid form instruction with L = 0.
Page 132 MPC850 does not support snooping an external bus activity outside the chip. The provision is made to cancel the reservation inside the MPC850 by using the CR and KR input signals. For accesses to internal resources, internal snoop logic monitors the internal bus for communication processor module (CPM) accesses of the address associated with the last lwarx instruction.
Page 133 Functionality Description Machine state The ﬂoating-point exception mode (bits FE0 and FE1) is ignored by the MPC850. The IP bit initial register state after reset is set as programmed by the reset conﬁguration speciﬁed in Section 6.1.2.1, “System Reset Interrupt (0x00100).”...
Page 134 The MPC850 MMU is described in detail in Chapter 8, “Memory Management Unit.” Reference and No reference bit is supported by the MPC850. However, the change bit is supported by using the change bits data TLB error exception mechanism when writing to an unmodiﬁed page.
Page 135: Mpc850 Register Implementation
These include registers that are deﬁned by the PowerPC architecture and registers that are speciﬁc to the MPC850. This section does not include registers that are part of the communication processor module (CPM); these registers are described in Part V, “Communications Processor Module.”...
Page 136: Powerpc Registers—User Registers
Only mtcrf Condition register See Section 4.1.1.1.1, “Condition Register User (CR).” Table 4-2 lists SPRs deﬁned by the PowerPC architecture implemented on the MPC850. Table 4-2. User-Level PowerPC SPRs SPR Number Name Comments Serialize Access Decimal [5–9]...
Page 137 MPC850 Register Implementation The CR ﬁelds can be set in one of the following ways: • Speciﬁed ﬁelds of the CR can be set from a GPR by using the mtcrf instruction. • An mcrf instruction can move the contents of XER[0–3] to a CR ﬁeld.
Page 138: Time Base Registers
MPC850. 4.1.2 PowerPC Registers—Supervisor Registers All supervisor-level registers implemented on the MPC850 are SPRs, except for the machine state register (MSR), described in Table 4-5. Table 4-5. Supervisor-Level PowerPC Registers...
Page 139: Dar, Dsisr, And Bar Operation
MPC850 Register Implementation Table 4-6 lists supervisor-level SPRs deﬁned by the PowerPC architecture. Table 4-6. Supervisor-Level PowerPC SPRs SPR Number Name Comments Serialize Access Decimal SPR[5–9] SPR[0–4] See the Programming Environments 00000 10010 DSISR Write: Full sync Manual and Section 4.1.2.1, “DAR, Read: Sync relative to DSISR, and BAR Operation.”...
Page 140: Unsupported Registers
• Segment registers—The MPC850 does not support memory segments. 4.1.2.3 PowerPC Supervisor-Level Register Bit Assignments This section describes bit assignments of supervisor-level PowerPC registers implemented by the MPC850. For more details, see the Programming Environments Manual for 32-Bit Processors. 4.1.2.3.1 Machine State Register (MSR) The 32-bit machine state register (MSR) is used to conﬁgure such parameters as the...
Page 141 Floating-point available. 0 The processor prevents dispatch of ﬂoating-point instructions, including ﬂoating-point loads, stores, and moves. 1 The processor can execute ﬂoating-point instructions. (This setting is invalid on the MPC850) Machine check enable 0 Machine check exceptions are disabled. 1 Machine check exceptions are enabled.
Page 142: Processor Version Register
4.1.3 MPC850-Speciﬁc SPRs Table 4-2 and Table 4-9 list SPRs speciﬁc to the MPC850. Debug registers, which have additional protection, are described in Chapter 44, “System Development and Debugging.” MPC850 Family User’s Manual...
Page 143 MPC850 Register Implementation Supervisor-level registers are described in Table 4-9. Table 4-9. MPC850-Specific Supervisor-Level SPRs SPR Number Name Comments Serialize Access Decimal SPR[5–9] SPR[0–4] 00010 10000 See Section 6.1.5, “Recoverability Write after an Exception.” 00010 10001 Write 00010 10010 Write...
Page 144 MPC850 Register Implementation Table 4-9. MPC850-Specific Supervisor-Level SPRs (Continued) SPR Number Name Comments Serialize Access Decimal SPR[5–9] SPR[0–4] 11000 11010 MD_AP Section 8.8.10, “MMU Access Write (as a store) Protection Registers (MI_AP/MD_AP)” 11000 11011 MD_EPN Section 8.8.3, “IMMU/DMMU Write (as a store) Effective Page Number Register (Mx_EPN)”...
Page 145: Accessing Sprs
Register Initialization at Reset Table 4-10. MPC850-Specific Debug-Level SPRs (Continued) SPR Number Name Serialize Access Decimal SPR[5–9] SPR[0–4] 00100 11010 CMPG Write: Fetch sync Read: Sync relative to load/store operations 00100 11011 CMPH Write: Fetch sync Read: Sync relative to load/store operations...
Page 146 • LCTRL1—Cleared. • LCTRL2—Cleared. • COUNTA[16–31]—Cleared. • COUNTB[16–31]—Cleared. • ICR—Cleared (no exception occurred). • DER[2,14,28–31]—Set (all debug-speciﬁc exceptions cause debug mode entry). Reset values for memory-mapped registers are provided with individual register descriptions throughout this manual. MPC850 Family User’s Manual...
Page 147: Operand Conventions
This section describes the operand conventions as they are represented in two levels of the PowerPC architecture. It also provides detailed descriptions of conventions used for storing values in registers and memory, accessing the MPC850’s registers, and representation of data in these registers.
Page 148: Instruction Set Summary
The frequent use of misaligned accesses is discouraged since they can compromise the overall performance of the processor. 5.2 Instruction Set Summary This section describes instructions and addressing modes deﬁned for the MPC850. These instructions are divided into the following functional categories: • Integer instructions—These include arithmetic and logical instructions. For more information, see Section 5.2.4.1, “Integer Instructions.”...
Page 149: Classes Of Instructions
Note that this grouping of instructions does not necessarily indicate the execution unit that processes a particular instruction or group of instructions. This information, which is useful in taking full advantage of the MPC850’s parallel instruction execution, is provided in Chapter 8, “Instruction Set,” in The Programming Environments Manual.
Page 150: Illegal Instruction Class
Deﬁned instructions are guaranteed to be supported in all PowerPC implementations, except as stated in the instruction descriptions in Chapter 8, “Instruction Set,” in The Programming Environments Manual. The MPC850 provides hardware support for all instructions deﬁned for 32-bit implementations, except ﬂoating-point instructions.
Page 151: Reserved Instruction Class
The following types of instructions are included in this class: • Implementation-speciﬁc instructions • Optional instructions deﬁned by the PowerPC architecture but not implemented by the MPC850 (for example, Floating Square Root (fsqrt) and Floating Square Root Single (fsqrts) instructions) 5.2.2 Addressing Modes This section provides an overview of conventions for addressing memory and for calculating effective addresses as deﬁned by the PowerPC architecture for 32-bit...
Page 152: Effective Address Calculation
• Previous instructions complete execution in the context (privilege, protection, and address translation) under which they were issued. • The instructions following the sc or rﬁ instruction execute in the context established by these instructions. MPC850 Family User’s Manual...
Page 153: Execution Synchronization
MSR[PR] bit indicates user mode. 5.2.2.3.3 Instruction-Related Exceptions There are two kinds of exceptions in the MPC850—those caused directly by the execution of an instruction and those caused by an asynchronous event. Either may cause components of the system software to be invoked.
Page 154: Powerpc Uisa Instructions
Integer instructions use the content of the GPRs as source operands and place results into GPRs, into the XER, and into condition register (CR) ﬁelds. 5.2.4.1.1 Integer Arithmetic Instructions Table 5-2 lists the integer arithmetic instructions for the MPC850. Table 5-2. Integer Arithmetic Instructions Name...
Page 155: Integer Compare Instructions
Implementation Note: In these instructions, the L bit is applicable for 64-bit implementations. For the MPC850, if L = 1 the instruction form is invalid. The core ignores this bit and, therefore, the behavior when L = 1 is identical to the valid form instruction with L = 0.
Page 156: Integer Logical Instructions
Integer rotate instructions rotate the contents of a register. The result of the rotation is either inserted into the target register under control of a mask (if a mask bit is 1 the associated bit MPC850 Family User’s Manual...
Page 157: Load And Store Instructions
See Section 5.2.2.2, “Effective Address Calculation,” for information about calculating effective addresses. Note that the MPC850 is optimized for load and store operations that are aligned on natural boundaries, and operations that are not naturally aligned may suffer performance degradation.
Page 158: Register Indirect Integer Load Instructions
• If rS = rA, the contents of rS are copied to the target memory element, then the generated EA is placed into rA (rS). The MPC850 deﬁnes store with update instructions with rA = 0 and integer store instructions with the CR update option enabled (Rc[31] = 1) to be invalid forms. Table 5-8 lists integer store instructions for the MPC850.
Page 159: Integer Load And Store With Byte-Reverse Instructions
When the MPC850 is operating with little-endian byte order, execution of a load or store multiple instruction causes the system alignment error handler to be invoked; see “Byte Ordering”...
Page 160: Integer Load And Store String Instructions
ﬁelds. When the MPC850 is operating with little-endian byte order, execution of a load or store string instruction causes the system alignment error handler to be invoked; see “Byte Ordering”...
Page 161: Branch Instruction Address Calculation
See Appendix F, “Simpliﬁed Mnemonics,” in The Programming Environments Manual for a list of simpliﬁed mnemonics. Chapter 5. MPC850 Instruction Set...
Page 162: Condition Register Logical Instructions
Note that if the LR update option is enabled for any of these instructions, these forms of the instructions are invalid in the MPC850. 5.2.4.4 Trap Instructions The trap instructions shown in Table 5-14 are provided to test for a speciﬁed set of conditions.
Page 163: Processor Control Instructions
(CR), machine state register (MSR), and special-purpose registers (SPRs), and to read from the time base register (TBU or TBL). 5.2.4.5.1 Move to/from Condition Register Instructions Table 5-15 lists the instructions provided by the MPC850 for reading from or writing to the Table 5-15. Move to/from Condition Register Instructions Name...
Page 164 However, in reality, other processors may have read from the location during this operation. In the MPC850, the reservations are made on behalf of aligned 16-byte sections of the memory address space.
Page 165: Powerpc Vea Instructions
However, the MPC850 does not support this enforcement of coherency in a multiprocessor system, and it broadcasts no special synchronization signal.
Page 166: Memory Synchronization Instructions—Vea
(which means all instructions that were in the instruction queue need to be refetched). In the MPC850, fetching an isync instruction causes fetch to stall, so that no refetching is required. On the MPC850, writes to SPRs and MSR that effect context are automatically context synchronizing, so an isync is not required before these instructions.
Page 167: Memory Control Instructions—Vea
The MMU translates the EA and the associated instruction Invalidate cache block is invalidated if hit. 5.2.6 PowerPC OEA Instructions The PowerPC OEA includes the structure of the memory management model, supervisor-level registers, and the exception model. Chapter 5. MPC850 Instruction Set...
Page 168: System Linkage Instructions
(CR), machine state register (MSR), and special-purpose registers (SPRs), and to read from the time base register (TBU or TBL). 5.2.6.2.1 Move to/from Machine State Register Instructions Table 5-15 lists the instructions provided by the MPC850 for reading from or writing to the MSR. Table 5-21. Move to/from Machine State Register Instructions...
Page 169: Memory Control Instructions—Oea
Instruction Set Summary 5.2.6.3 Memory Control Instructions—OEA This section describes memory control instructions, which include the following types: • Cache management instructions • TLB management instructions Chapter 5. MPC850 Instruction Set...
Page 170 Instruction Set Summary MPC850 Family User’s Manual...
Page 171 Chapter 6 Exceptions Core exceptions can be generated when an exception condition occurs. Exception sources in the MPC850 include the following: • External interrupt request • Certain memory access conditions (protection faults and bus errors) • Internal errors, such as an attempt to execute an unimplemented opcode •...
Page 172: Exceptions
6.1 Exceptions The OEA deﬁnes a set of exceptions for PowerPC processors, some of which are optional. The following sections describe exceptions implemented on the MPC850. Those deﬁned by the OEA are described in Section 6.1.2, “PowerPC-Deﬁned Exceptions.” Section 6.1.3, “Implementation-Speciﬁc Exceptions,”...
Page 173: Exception Ordering
Offset Exception Description 0x00800 Floating-point unavailable The MPC850 cannot generate a ﬂoating-point exception. Attempting to execute a ﬂoating-point instruction causes an implementation-speciﬁc software emulation exception (see Section 6.1.3.1, “Software Emulation Exception (0x01000)”) regardless of the setting of MSR[FP]. 0x00900 Decrementer See Section 6.1.2.8, “Decrementer Exception (0x00900).”...
Page 174 Signal from the interrupt controller Decrementer interrupt (masked if MSR[EE] = 0) Decrementer request 6.1.2 PowerPC-Deﬁned Exceptions The following sections describe the exceptions as they are deﬁned by the OEA, and describes how they are implemented on the MPC850. MPC850 Family User’s Manual...
Page 175: System Reset Interrupt (0X00100)
Exceptions 6.1.2.1 System Reset Interrupt (0x00100) A system reset interrupt occurs when IRQ0 is asserted. When the exception is taken, processing begins at offset 0x00100. A hard or soft reset also causes program execution to begin fetching at 0x00100 after the associated reset actions. Table 6-4 shows register settings.
Page 176: Dsi Exception (0X00300)
ITLB error interrupt. 6.1.2.5 External Interrupt Exception (0x00500) In the MPC850 the external interrupt is generated by the on-chip interrupt controller. It is software acknowledged and maskable by MSR[EE], which hardware clears automatically to disable external interrupts when any exception is taken.
Page 177: Alignment Exception (0X00600)
Exceptions • or, one bus cycle for aligned access • or, two bus cycles for unaligned access System-level exception latency can be longer than the interval from B to E. If an instruction ahead of the exception-causing instruction also generates an exception, that exception is recognized ﬁrst.
Page 178: Integer Alignment Exceptions
More speciﬁcally, these operations may either cause an alignment exception or they may cause the processor to break the memory access into multiple, smaller accesses with respect to the cache and the memory subsystem. MPC850 Family User’s Manual...
Page 179: Program Exception (0X00700)
Exceptions 6.1.2.7 Program Exception (0x00700) A program exception occurs when no higher priority exception exists and one or more of the following exception conditions, which correspond to bit settings in SRR1, occur during execution of an instruction: • An lswx instruction for which rA or rB is in the range of registers to be loaded (may cause results that are boundedly undeﬁned) •...
Page 180: Decrementer Exception (0X00900)
A system call exception occurs when a System Call (sc) instruction is executed. The effective address of the instruction following the sc instruction is placed into SRR0. MSR bits are saved in SRR1, as shown in Table 6-10. Then a system call exception is generated. MPC850 Family User’s Manual...
Page 181: Trace Exception (0X00D00)
Exceptions The system call exception causes the next instruction to be fetched from offset 0x00C00 from the physical base address indicated by the new setting of MSR[IP]. As with most other exceptions, this exception is context-synchronizing. Refer to Section 5.2.2.3.1, “Context Synchronization,”...
Page 182: Floating-Point Assist Exception
Exceptions 6.1.2.11 Floating-Point Assist Exception The ﬂoating-point assist exception is not generated by the MPC850. Attempting to execute a ﬂoating-point causes an instruction implementation-speciﬁc software emulation exception. 6.1.3 Implementation-Speciﬁc Exceptions The following sections describe the MPC850’s implementation-speciﬁc exceptions. 6.1.3.1 Software Emulation Exception (0x01000) An software emulation exception occurs as a result of one of the following conditions: •...
Page 183: Data Tlb Miss Exception (0X01200)
• The EA cannot be translated. Either the segment or page valid bit of this page is cleared in the translation table. Note that although the MPC850 does not implement segment registers as they are deﬁned by the OEA, the concept of segment is retained as the memory space accessible to the level-one table descriptors.
Page 184: Data Tlb Error Exception (0X014000)
Set to the EA of the instruction that caused the exception. SRR1 1–40 10–150 OtherLoaded from MSR[16-31]. SRR1[30] is cleared only by loading a zero from MSR[RI]. IP No change MENo change LECopied from the ILE setting of the interrupted process Others0 MPC850 Family User’s Manual...
Page 185: Debug Exceptions (0X01C00–0X01F00)
Exceptions Table 6-16. Register Settings after a Data TLB Error Exception (Continued) Register Setting DSISR 1 Set if the translation of an attempted access is not found in the translation tables. Otherwise, cleared 2–30 4 Set if the memory access is not permitted by the protection mechanism; otherwise cleared 6 1 for a store operation;...
Page 186: Implementing The Precise Exception Model
The following instructions may cause the completion queue to ﬁll: • Integer divide instructions • Instructions that affect or use resources external to the core (load/store instructions, and especially load/store string multiple/instructions) MPC850 Family User’s Manual...
Page 187: Recoverability After An Exception
Exceptions 6.1.5 Recoverability after an Exception The processor cannot always recover from system reset and machine check interrupts, either because the conditions that cause the interrupt are catastrophic or because they caused the save/restore information in SRR0 and SRR1to be overwritten. All other PowerPC exceptions should be restartable.
Page 188: Exception Latency
6.1.6 Exception Latency Figure 6-1 describes signiﬁcant events during exception processing. ••• Stage Fetch (in IQ) In dispatch entry (IQ0) Execute Complete (In CQ) In retirement entry (CQ0) Instruction Queue Completion Queue Figure 6-1. Exception Latency MPC850 Family User’s Manual...
Page 189 Exceptions Table 6-19. Exception Latency Kill Time Point Fetch Issue Instruction Complete Pipeline Faulting instruction issue Instruction complete and all previous instructions complete Start fetch handler Kill pipeline D (at least 3 clocks after B) First instruction of handler dispatched A At time point A the excepting instruction dispatches and begins executing.
Page 190: Partially Completed Instructions
Next instruction to execute Debug I- breakpoint Before Faulting instruction Debug L- breakpoint Load/store After Faulting instruction + 4 Software emulation Before Faulting instruction Floating-point unavailable Floating-point Before Faulting instruction Implementation-speciﬁc exceptions not deﬁned by the PowerPC architecture MPC850 Family User’s Manual...
Page 191 Chapter 7 Instruction and Data Caches The MPC850 contains separate, two-way set associative (2-Kbyte) and data (1-Kbyte) caches to allow rapid core access to instructions and data. This chapter describes the organization of the on-chip instruction and data caches, cache control, various cache operations, and the interaction between the caches, the load/store unit (LSU), the instruction sequencer, and the system interface unit (SIU).
Page 192: Instruction Cache Organization
Instruction Cache Organization On a cache miss, the MPC850’s cache blocks are ﬁlled in 16-byte bursts. The burst ﬁll is performed as a critical-word-ﬁrst operation; the critical word is simultaneously written to the cache and forwarded to the requesting unit, thus minimizing stalls due to cache ﬁll latency.
Page 193 Bidirectional multiplexer 2 -> 1 To block buffer/ From burst buffer Figure 7-1. MPC850 Instruction Cache Organization Each instruction cache block contains four contiguous words from memory that are loaded from a four-word boundary; that is, bits A[28–31] of the logical (effective) addresses are zero.
Page 194: Data Cache Organization
7.2 Data Cache Organization The MPC850 data cache is organized as 32 sets of two blocks as shown in Figure 7-2. Each block consists of 4 words, two state bits, a lock bit, and an address tag. MPC850 Family User’s Manual...
Page 195 Note that address bits A[23–27] provide the index to select a cache set for the MPC850. Bits A[28–31] select a byte within a block. The tags consist of the high-order physical address bits PA[0–22]. Address translation occurs in parallel with set selection (from A[23–27]).
Page 196: Cache Control Registers
The data cache also implements a lock bit for each cache block that allows data to be loaded into the data cache and locked. The MPC850 supports commands for locking and unlocking individual cache blocks and for unlocking all the cache blocks at once.
Page 197 Instruction cache error type 1—bus error during an IC_CST load & load cache block command 0 No error detected 1 Error detected Note that this is a read-only, sticky bit, set only by the MPC850 when an error is detected. Reading this bit clears it. CCER2 Instruction cache error type 2—no unlocked way available for an IC_CST load &...
Page 198: Reading Data And Tags In The Instruction Cache
7.3.1.1 Reading Data and Tags in the Instruction Cache The MPC850 supports reading the data, tags, and the state and lock bits stored in the instruction cache. The instruction cache read command, issued by reading the IC_DAT register, uses the IC_ADR register to qualify what is to be read. Table 7-4 describes the ﬁelds of the IC_ADR register during an instruction cache read command.
Page 199: Ic_Cst Commands
(IC_CST[IEN]). When disabled, the MPC850 ignores the instruction cache valid bit and operates as if all accesses have caching-inhibited access attributes (that is, all instruction fetches are propagated to the bus as single-beat transactions).
Page 200: Instruction Cache Unlock Cache Block Command
& lock cache block commands before checking the termination status. These bits are set by the MPC850 and are cleared by software. Note that the MPC850 considers all zero-wait-state devices on the internal bus as caching-inhibited. For this reason, software should not perform load & lock cache block operations from these devices on the internal bus.
Page 201: Instruction Cache Unlock All Command
The instruction cache performs the invalidate all command in one clock cycle. 7.3.2 Data Cache Control Registers The MPC850 implements three special purpose registers (SPRs) to control the data cache—the data cache control and status register (DC_CST), the data cache address register (DC_ADR), and the data cache data port register (DC_DAT).
Page 202 SIU unmunges the address and swaps the bytes of data within each word at the external bus/internal U-bus boundary. See Appendix A, “Byte Ordering,” for more information on MPC850 byte ordering. Note that this is a read-only bit. Any attempt to write to it is ignored. This bit is programmed by issuing the appropriate command in DC_CST[CMD].
Page 203 0 No error detected 1 Error detected Note that this is a read-only, sticky bit, set only by the MPC850 when an error is detected. Reading this bit clears it. CCER2 Data cache error type 2. This bit indicates one of two possible errors—either a bus error during DC_CST load &...
Page 204: Reading Data Cache Tags And Copyback Buffer
7.3.2.1 Reading Data Cache Tags and Copyback Buffer The MPC850 supports reading the tags, the state bits and the lock bits stored in the data cache as well as the last copyback address, and data words in the copyback buffer. The data cache read command, issued by reading DC_DAT, uses the DC_ADR register to qualify what is to be read.
Page 205: Dc_Cst Commands
Cache Control Registers To read the copyback buffer data or the tags stored in the data cache, do the following: 1. Write the address of the copyback buffer or tag to be read to the DC_ADR according to the format shown in Table 7-9. Note that it is also possible to read this register for debugging purposes.
Page 206: Data Cache Enable/Disable Commands
(DC_CST[DEN]). When disabled, the MPC850 ignores the data cache state bits and operates as if all accesses have caching-inhibited access attributes (that is, all accesses are propagated to the bus as single-beat transactions).
Page 207: Data Cache Unlock Cache Block Command
Cache Control Registers 7.3.2.2.3 Data Cache Unlock Cache Block Command The unlock cache block command (DC_CST[CMD] = 0b1000) is used to unlock previously locked cache blocks. To unlock a cache block: 1. Write the address of the cache block to be unlocked to the DC_ADR register. 2.
Page 208: Powerpc Cache Control Instructions
Note that the MPC850 does not broadcast cache control instructions nor does it snoop such broadcasts. A TLB miss exception is generated if the effective address of one of these instructions cannot be translated and data address relocation is enabled.
Page 209: Data Cache Block Zero (Dcbz)
MPC850). The MPC850 loads the data into the cache when the effective address hits in the TLB, is permitted load access from the addressed page, and is directed at a caching-allowed page.
Page 210: Data Cache Block Flush (Dcbf)
An instruction cache access begins with an instruction fetch request from the instruction sequencer in the PowerPC core. As shown in Figure 7-1, bits 22–27 of the instruction address provide the index to select a set (0–63) within the instruction cache array. The tags MPC850 Family User’s Manual...
Page 211 Note that if one of these buffers contains the requested instruction, it is also considered a cache hit. To minimize power consumption, the MPC850 can detect that one of the buffers contains the requested instruction and service the instruction request from the buffers without activating the instruction cache array.
Page 212: Instruction Cache Hit
• Instruction fetch latency is reduced by sending the requested instruction address to the instruction cache and internal bus simultaneously. A cache hit aborts the internal bus transaction before the MPC850 can initiate an external fetch. • The instruction cache supports stream hits (allows fetching from the burst buffer or directly from the internal data bus, before the instruction cache array is ﬁlled)
Page 213: Instruction Fetching On A Predicted Path
It is also considered a programming error to perform load & lock cache block operations from zero wait state devices that are located on the internal bus. The MPC850 considers these devices as caching-inhibited memory regions. If a load & lock cache block operation is performed from such a device, the instruction is not guaranteed to be fetched from the instruction cache;...
Page 214: Updating Code And Memory Region Attributes
(modiﬁed-valid/unmodiﬁed-valid/invalid) protocol. The MPC850 does not support snooping of the data cache. All memory is considered to have memory coherency not required attributes. Therefore, software must maintain data cache coherency. The MPC850 does not provide support for snooping external bus activity. All coherency between the internal caches and external agents (memory or I/O devices) must be controlled by MPC850 Family User’s Manual...
Page 215: Data Cache Load Hit
In addition, there is no mechanism provided for DMA or other internal masters to access the data cache directly. The MPC850 data cache includes the following operational features: • Single-cycle cache access on hit and one clock latency added for miss •...
Page 216: Write-Through Mode
If the store hit is to a unmodiﬁed-valid cache block, then data is stored in the cache block and the block is marked modiﬁed-valid. In either case, the LRU state of the set is updated to reﬂect the hit. MPC850 Family User’s Manual...
Page 217: Data Cache Store Miss In Write-Back Mode
Data Cache Operation 7.6.4.2 Data Cache Store Miss in Write-Back Mode In the case of a data cache store miss in write-back mode, the data cache must establish the block in the cache array before modifying that block. Therefore, a block in the cache array is selected to receive the data from memory and from the load/store unit.
Page 218: Atomic Memory References
MPC850 does not snoop external bus activity, provision is made to cancel a reservation inside the MPC850 by using the and KR input signal. The state of the reservation is always presented onto the RSV output signal. This can be used by external agents to determine when an internal condition has caused a change in the reservation state.
Page 219: Cache Initialization After Reset
0 of each set. 7.8 Debug Support The MPC850 can be debugged either in debug mode or by a software monitor debugger. In both cases the core of the MPC850 asserts the internal freeze signal. See Chapter 44, “System Development and Debugging,”...
Page 220: Instruction And Data Cache Operation In Debug Mode
MPC850 core. Therefore, the instruction cache is bypassed when the MPC850 is in debug mode. In addition, the data cache is frozen in debug mode. Loads and stores in debug mode always target system memory, regardless of whether the accessed data is resident in the data cache.
Page 221 Debug Support 4. Unlock any ways of the original sets that were not previously locked 5. To restore the old state of the LRU bits make sure that the last access (load & lock cache block or unlock cache block command) is performed on the most-recently used way (not the LRU way).
Page 222 Debug Support MPC850 Family User’s Manual...
Page 223: Features
4-, 16-, 512-Kbyte, or 8-Mbyte pages or 1-Kbyte subpages (for 4-Kbyte pages only). The MPC850 has separate instruction and data MMUs. The preﬁx Mx_ indicates a reference to both the instruction and data (MI_ and MD_) versions of the register.
Page 224: Powerpc Architecture Compliance
— 1 clock penalty for other TLB hit instruction accesses • Low power consumption 8.2 PowerPC Architecture Compliance The MPC850 core complies largely with the MMU as it is deﬁned by the OEA, with the following differences: • The MPC850 does not implement the following PowerPC features: —...
Page 225: Address Translation
Recently used translations are kept in translation lookaside buffers (TLBs) in hardware. In the MPC850, software handles the table lookup and TLB reload with little hardware assistance. This offers a ﬂexible translation table structure choice, because many systems would not beneﬁt from a full-featured hardware translation mechanism.
Page 226 DMMU does not implement a fast TLB mechanism. The DTLB is accessed for each transfer simultaneously with the data cache tag read, hence there is no time penalty. MPC850 Family User’s Manual...
Page 227: Tlb Operation
Address Translation Data/Instruction Fetch 32-bit EA is generated Compare address with TLB (0 clock penalty) entries Is page TLB error exception valid TLB reload (read page Access permitted description from external by page protection memory to TLB) (20–23 clock penalty @ one wait-state external memory) Use page description from TLB...
Page 228: Using Access Protection Groups
Mx_AP ﬁelds to 01. In PowerPC mode, each ﬁeld holds the Kp and Ks bits for the corresponding segment deﬁned by the level-one table descriptor. In domain manager mode, each ﬁeld holds override information over the page protection setting—no override, no access override, and free access override. MPC850 Family User’s Manual...
Page 229: Protection Resolution Modes
Protection Resolution Modes 8.5 Protection Resolution Modes The MMUs can be programmed in three different modes that have different methods of deﬁning the protection resolution of the address space. These are as follows: • Mode 1—Protection resolution to 4-Kbyte minimum page size. This is the simplest mode with the most efﬁcient memory size (that is, MMU tables are smaller).
Page 230: Memory Attributes
Memory attributes deﬁned by the PowerPC architecture are implemented as follows: • Reference and change bit updates—The MPC850 does not generate an exception for an R (reference) bit update. In fact, there is no entry for an R bit in the TLB.
Page 231: Translation Table Structure
Translation Table Structure The G attribute is used to map I/O devices that are sensitive to speculative (out-of-order) accesses. An attempted speculative access to a page marked guarded (G = 1) stalls until either the access is nonspeculative or is canceled by the core. Attempting to fetch from guarded memory causes an implementation-speciﬁc instruction TLB error interrupt.
Page 232 EA[10–19]. For 16 Kbyte pages, this requires that multiple identical level-two descriptors be provided. This is summarized in Table 8-1. Figure 8-5 shows the two-level translation table when MD_CTR[TWAM] = 0 (1 Kbyte resolution of protection). MPC850 Family User’s Manual...
Page 233 Translation Table Structure Effective Address Level-1 Table Pointer (M_TWB) Level-1 Index Level-2 Index Page Offset 18-Bit 12-Bit Level-1 Table Base Level-1 Index Level-1 Table 18-Bit 12-Bit Level-1 Descriptor 0 12 for 1 Kbyte 12 for 4 Kbyte Level-1 Descriptor 1 14 for 16 Kbyte 10-Bit 19 for 512 Kbyte...
Page 234: Level-One Descriptor
01 512 Kbyte 10 Reserved 11 8 Mbyte Writethrough attribute for entry 0 Copyback cache policy region (default) 1 Writethrough cache policy region Level-one segment valid bit 0 Segment is not valid 1 Segment is valid MPC850 Family User’s Manual...
Page 235: Level-Two Descriptor
Translation Table Structure 8.7.2 Level-Two Descriptor Table 8-4 describes the level-two descriptor format supported by hardware. (Section 8.5, “Protection Resolution Modes,” describes the protection modes.) Table 8-4. Level-Two (Page) Descriptor Format Bits Name Mode 2 Mode 1 or Mode 3 0–19 Physical (real) page number 20–21 PP...
Page 236: Page Size
MSR[IR] = 0 and MSR[DR] = 0. No similar restriction exists for tlbie and tlbia. Table 8-6 lists the MPC850-speciﬁc MMU registers and indicates the sections that describe them. These SPRs should be accessed when both instruction and data address translation is disabled.
Page 237: Immu Control Register (Mi_Ctr)
Programming Model Table 8-6. MPC850-Specific MMU SPRs (Continued) Register Name Section M_TWB MMU tablewalk base register 8.8.8 Protection Registers M_CASID CASID register 8.8.9 MI_AP IMMU access protection register 8.8.10 MD_AP DMMU access protection register Scratch Register M_TW MMU tablewalk special register 8.8.11...
Page 238: Dmmu Control Register (Md_Ctr)
The DMMU control register (MD_CTR), shown in Figure 8-7, controls DMMU operation. Field GPM PPM CIDEF WTDEF RSV2D TWAM PPCS — Reset 0000_0 0_0000_0000 Field — DTLB_INDX — Reset 0x0000 Figure 8-7. DMMU Control Register (MD_CTR) MPC850 Family User’s Manual...
Page 239: Immu/Dmmu Effective Page Number Register (Mx_Epn)
Programming Model Table 8-8 describes MD_CTR ﬁelds. Table 8-8. MD_CTR Field Descriptions Bits Name Description Group protection mode 0 PowerPC mode 1 Domain manager mode Page protection mode 0 Page resolution of protection 1 1-Kbyte resolution of protection for 4-Kbyte pages CIDEF CI default when the DMMU is disabled (MSR[DR] = 0) 0 Caching is allowed.
Page 240: Immu Tablewalk Control Register (Mi_Twc)
Guarded memory attribute for entry 0 Nonguarded memory (default for ITLB miss) 1 Guarded memory 28–29 Page size level-one 00 Small (4 or 16 Kbyte. See MI_RPN[SPS]) Default for ITLB miss 01 512 Kbyte 10 Reserved 11 8 Mbyte MPC850 Family User’s Manual...
Page 241: Dmmu Tablewalk Control Register (Md_Twc)
Programming Model Table 8-10. MI_TWC Field Descriptions (Continued) Bits Name Description — Reserved. Ignored on write. Returns 0 on read. Entry valid bit 0 Entry is not valid 1 Entry is valid. Default value on ITLB miss. 8.8.5 DMMU Tablewalk Control Register (MD_TWC) The DMMU tablewalk control register (MD_TWC), shown in Figure 8-10, contains the level-two pointer and access protection group of an entry to be loaded into the TLB.
Page 242: Immu Real Page Number Register (Mi_Rpn)
TLB. MI_RPN should be written after MI_EPN and MI_TWC are written. Field Reset — Field Reset — Figure 8-11. IMMU Real Page Number Register (MI_RPN) MPC850 Family User’s Manual...
Page 243: Dmmu Real Page Number Register (Md_Rpn)
Programming Model Table 8-12 describes MI_RPN ﬁelds. (Section 8.5, “Protection Resolution Modes,” describes the protection modes.) Table 8-12. MI_RPN Field Descriptions Bits Name Mode 2 Mode 1 or Mode 3 0–19 Real (physical) page number 20–21 Protection attributes for Extended Encoding: PowerPC Encoding: subpages 1–4.
Page 244 Cache-inhibit attribute for the entry. 0 Caching is allowed. 1 Caching is inhibited. Entry valid indication. For pages larger than 4 Kbytes in mode 2, PP in bits [22–23,24–25,26–27] must equal the PP in bits [20–21]. MPC850 Family User’s Manual...
Page 245: Mmu Tablewalk Base Register (M_Twb)
Programming Model 8.8.8 MMU Tablewalk Base Register (M_TWB) The MMU tablewalk base register (M_TWB), shown in Figure 8-13, contains a pointer to the level-one table to be used in hardware-assisted tablewalk mode. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field L1TB L1TB...
Page 246: Mmu Debug Registers
RAM values of the entry indexed by DTLB_INDX to MX_CAM, MX_RAM0, and MX_RAM1. Any register can be the source for mtspr since its value is not used. The values of MX_CAM, MX_RAM0, and MX_RAM1 can be read using mfspr; mtspr[MX_RAM0] and mtspr[MX_RAM1] are considered no-ops. MPC850 Family User’s Manual...
Page 247: Immu Cam Entry Read Register (Mi_Cam)
Programming Model 8.8.12.1 IMMU CAM Entry Read Register (MI_CAM) Figure 8-17 shows the MMU instruction CAM entry read register (MI_CAM). When the content-addressable memory of the MI_CAM register is read, it contains the effective address and page sizes of an entry indexed by MI_CTR[ITLB_INDX]. MI_CAM is updated only by writing to it.
Page 248: Immu Ram Entry Read Register 0 (Mi_Ram)
0 Subpage 2 (Address[20–21] = 10) Supervisor fetch is not permitted 1 Subpage 2 (Address[20–21] = 10) Supervisor fetch is permitted 0 Subpage 3 (Address[20–21] = 11) Supervisor fetch is not permitted 1 Subpage 3 (Address[20–21] = 11) Supervisor fetch is permitted MPC850 Family User’s Manual...
Page 249: Immu Ram Entry Read Register 1 (Mi_Ram)
Programming Model 8.8.12.3 IMMU RAM Entry Read Register 1 (MI_RAM1) The IMMU RAM entry read register 1 (MI_RAM1), shown in Figure 8-19, contains the protection mode information of the entry indexed by MI_CTR[ITLB_INDX]. This register is updated only when MI_CAM is written to. Field —...
Page 250: Dmmu Ram Entry Read Register 0 (Md_Ram0)
The DMMU RAM entry read register 0 (MD_RAM0), shown in Figure 8-21, contains the physical page number and page attributes of an entry indexed by MD_CTR[DTLB_INDX]. This register is updated when any value is written to MD_CAM. MPC850 Family User’s Manual...
Page 251: Dmmu Ram Entry Read Register 1 (Md_Ram1)
Programming Model Field Reset — Field APGI — Reset — Figure 8-21. DMMU RAM Entry Read Register 0 (MD_RAM0) Table 8-21 describes MD_RAM0 ﬁelds. Table 8-21. MD_RAM0 Field Descriptions Bits Name Description 0–19 Real (physical) page number 20–22 PS Page size. (Values not shown are reserved) 000 4 Kbyte 001 16 Kbyte 011 512 Kbyte...
Page 252 0 Subpage 1 (address[20–21] = 01) User read access is not permitted 1 Subpage 1 (address[20–21] = 01) User read access is permitted UWP1 0 Subpage 1 (address[20–21] = 01) User write access is not permitted 1 Subpage 1 (address[20–21] = 01) User write access is permitted MPC850 Family User’s Manual...
Page 253: Memory Management Unit Exceptions
0 Subpage 3 (address[20–21] = 11) User write access is not permitted 1 Subpage 3 (address[20–21] = 11) User write access is permitted 8.9 Memory Management Unit Exceptions Table 8-23 describes MPC850-speciﬁc MMU exceptions. Table 8-23. MPC850-Specific MMU Exceptions Exception...
Page 254: Tlb Reload
R1, MD_TWC # Load R1 with level-2 pointer while taking page # size into account R1, (R1) # Load level-2 page entry mtspr MD_RPN, R1 # Write TLB entry mfspr R1, M_TW # Restore R1 Figure 8-23. DTLB Reload Code Example MPC850 Family User’s Manual...
Page 255: Locking Tlb Entries
TLB Manipulation Figure 8-24 performs an ITLB reload itlb_swtw mtspr M_TW, R1 # Save R1 mfspr R1, SRR0 # Load R1 with instruction miss EA (the same data # may be taken from MI_EPN) mtspr MD_EPN, R1 # Save instruction miss EA in MD_EPN mfspr R1, M_TWB # Load R1 with level-1 pointer R1, (R1)
Page 256: Loading Locked Tlb Entries
MD_CTR[DTLB_INDX] or MI_CTR[ITLB_INDX], negating MD_EPN[EV] or MI_EPN[EV], and writing to the appropriate MD_RPN or MI_RPN. The TLBs are not invalidated automatically on reset, but are disabled. However, they must be invalidated under program control during initialization. MPC850 Family User’s Manual...
Page 257: Instruction Execution Timing Examples
Chapter 9 Instruction Execution Timing This chapter describes the timing of PowerPC instructions that execute in the core. Examples show stalls and bubbles due to serialization, latency, and blockage. 9.1 Instruction Execution Timing Examples The following sections provide timings for the following scenarios: •...
Page 258: Writeback Arbitration
GCLK1 mulli addic Fetch Decode mulli addic mulli sub, mulli addic Read + Execute addic mulli Writeback Figure 9-3. Writeback Arbitration Timing—Example 2 MPC850 Family User’s Manual...
Page 259: Private Writeback Bus Load
Instruction Execution Timing Examples 9.1.3 Private Writeback Bus Load In Figure 9-4, lwz and xor write back in the same clock since they use the writeback bus in two different ticks (a tick = 1/4 of a processor clock). r12,64 (SP) r5,r5,3 cror 4,14,1...
Page 260: A Full Completion Queue
BPU allows the two bubbles caused by the bl issue and execution to overlap the two bubbles caused by the load. Issuing bl causes a bubble because it does no work. r12,64 (SP) r3,r12,3 addic r4,r14,1 func func: mulli r5,r3,3 addi r4,3(r0) MPC850 Family User’s Manual...
Page 261: Branch Prediction
Instruction Execution Timing Examples GCLK1 addic mulli addi Fetch Bubble addic mulli Decode Read + Execute Bubble Bubble addic mulli addic Writeback L Address Drive L Data Load Writeback Branch Decode Branch Execute Figure 9-7. Branch Folding Timing 9.1.7 Branch Prediction In this example, the blt instruction is dependent on the cmpi instruction.
Page 262: Instruction Timing List
Integer load/store multiple: lmw, smw Serialize + 1 + no. of registers Synchronize: sync Serialize + 1 Memory synchronization: lwarx, stwcx. Serialize + 2 Move CR from XER: mcrxr Serialize + 1 MPC850 Family User’s Manual...
Page 263: Load/Store Instruction Timing
Instruction Timing List Table 9-1. Instruction Execution Timing (Continued) Instructions Latency Blockage Unit Serializing Move to/from SPR (Debug, DAR, DSISR): mtspr, mfspr Serialize + 1 String instructions: lswi, lswx, stswi, stswx. See Serialize + 1 + no. of words Section 9.2.2, “String Instruction Latency.” accessed Memory control instructions: isync Serialize...
Page 264: String Instruction Latency
See Section 4.1.3.1, “Accessing SPRs.” If the access ends in a bus error, a software emulation exception is taken. All write operations to off-core SPRs (mtspr) are previously synchronized. In other words, the instruction is not taken until all prior instructions terminate. MPC850 Family User’s Manual...
Page 265 Part III is intended for system designers and programmers who need to understand the operation of the MPC850 at start up. It assumes an understanding of the PowerPC programming model described in the previous chapters and a high level understanding of the MPC850.
Page 266 Data address register Decrementer register Direct memory access DRAM Dynamic random access memory DTLB Data translation lookaside buffer Effective address General-purpose register IEEE Institute of Electrical and Electronics Engineers ITLB Instruction translation lookaside buffer Least-signiﬁcant byte Least-signiﬁcant bit MPC850 Family User’s Manual...
Page 267 Table iv. Acronyms and Abbreviated Terms (Continued) Term Meaning Load/store unit Memory management unit Most-signiﬁcant byte Most-signiﬁcant bit Machine state register Peripheral component interconnect RISC Reduced instruction set computing RTOS Real-time operating system Receive Special-purpose register Software watchdog timer Time base register Translation lookaside buffer Transmit Part III.
Page 268 MPC850 Family User’s Manual...
Page 269 IEEE 1149.1 standard described in Chapter 45, “IEEE 1149.1 Test Access Port.” Note that the MPC850’s address bus is 26 bits wide, while the internal address bus is 32 bits wide. Therefore, external accesses are considered internally as 26-bit accesses (A[6–31]) with A[0–5] equal to 0, while internal accesses are full 32-bit accesses.
Page 270: Features
• PCMCIA host adapter module supports one slot with eight memory or I/O windows • IEEE 1149.1 test access port 10.2 System Conﬁguration and Protection The MPC850 incorporates many system functions that normally must be provided in external circuits. The following features provide maximum system safeguards against hardware and/or software faults: •...
Page 271: System Configuration And Protection
System Conﬁguration and Protection • PowerPC timebase counter—Provides a timebase reference for the operating system or application software. This 64-bit timebase counter is deﬁned by the PowerPC architecture and has two independent reference registers that generate a maskable interrupt when the programmed value in one of the registers is reached. The associated bit in the timebase status and control register (TBSCR) is set for the reference register that generated the interrupt.
Page 272: Multiplexing Siu Pins
Multiplexing SIU Pins 10.3 Multiplexing SIU Pins Due to the limited number of pins available in the MPC850 package, some of the functionalities share pins. Table 10-1 shows how functionality is controlled on each pin. Table 10-1. Multiplexing Control Name Pin Conﬁguration Control...
Page 273: Programming The Siu
Part number (read-only). Mask programmed with a code corresponding to the part number of the MPC850. Intended to help factory test and user code that is sensitive to part reﬁnements. PARTNUM would change if a new module is added or if the size of the memory module is revised.
Page 274: Siu Module Configuration Register (Siumcr)
1 Show address and data of all internal data cycles. 9–10 DBGC Debug pin conﬁguration. The default is set by the hard reset conﬁguration word. See Section 11.3.1.1, “Hard Reset Conﬁguration Word” for the description of these bits. MPC850 Family User’s Manual...
Page 275 If SEME = 1, the memory controller interprets any assertion of TS not driven by the MPC850 as a synchronous external master initiating a transaction. If SEME = 0, the memory controller ignores TS unless it is external bus master.
Page 276: System Protection Control Register (Sypcr)
1 The software watchdog timer stops counting when FRZ is asserted. Software watchdog enable. To disable the software watchdog timer, it should be cleared by the software after a system reset. 0 Software watchdog timer disabled. 1 Software watchdog timer enabled. (default) MPC850 Family User’s Manual...
Page 277: Transfer Error Status Register (Tesr)
Programming the SIU Table 10-4. SYPCR Field Descriptions (Continued) Bits Name Description SWRI Software watchdog reset/interrupt select. 0 The software watchdog timer causes an NMI (system reset interrupt) to the core. 1 The software watchdog timer causes an HRESET. (default) Software watchdog prescale.
Page 278: Register Lock Mechanism
SIU registers maintained by KAPWR against uncontrolled shutdown, a register locking mechanism is included. These registers can be write-protected in a set of associated key registers. The MPC850 key registers are shown in Table 10-6. Table 10-6. Key Registers...
Page 279: Interrupt Structure
Module Conﬁguration Register (SIUMCR).” 10.5.1 Interrupt Structure The SIU receives interrupts from internal sources, like the PIT, real-time clock, communications processor module (CPM), and the external IRQ pins. Figure 10-7 shows the MPC850 interrupt structure. Chapter 10. System Interface Unit...
Page 280 Level 0 Debug Debug Figure 10-7. MPC850 Interrupt Structure If programmed to generate interrupts, the software watchdog timer generates a nonmaskable system reset interrupt (NMI) to the core. Asserting the external IRQ0 pin generates an NMI as well. Note that the core takes the system reset interrupt vector when an NMI is asserted and jumps to the external interrupt vector when any other interrupt is asserted by the interrupt controller.
Page 281: Priority Of Interrupt Sources
System Conﬁguration 10.5.2 Priority of Interrupt Sources There are eight external IRQ pins (IRQ0 is essentially nonmaskable, although in a limited sense it can be masked as shown in Table 10-8) and eight interrupt levels. Asserting IRQ0 causes an NMI. The other 15 interrupt sources assert a single interrupt request to the core (the external interrupt).
Page 282: Siu Interrupt Processing
10.5.3.1 Nonmaskable Interrupts—IRQ0 and SWT Figure 10-9 is a logical representation of IRQ0. SIEL[ED0] SIEL[ED0] Level Level IRQ0 Edge Edge SIPEND[IRQ0] SIPEND[IRQ0] = 1 Figure 10-9. IRQ0 Logical Representation Table 10-8 describes the differences between IRQ0 and other IRQ interrupts. MPC850 Family User’s Manual...
Page 283: Programming The Siu Interrupt Controller
System Conﬁguration Table 10-8. IRQ0 Versus IRQx Operation Functionality IRQ0 IRQx Exception Vector 0x100 0x500 Core input External interrupt SIMASK Not used, except for enabling SIVEC Used for masking SIVEC Not normally used. If used, SIMASK[IRQ0] Supplies the interrupt code so the core knows must be set.
Page 284 Note that IRQ0 can be masked in only a very limited sense. If SIEL[ED0] = 1, edge-sensitive, and SIPEND[IRQ0] is not cleared in the interrupt service routine, further assertions of IRQ0 are masked. MPC850 Family User’s Manual...
Page 285: Siu Interrupt Mask Register (Simask)
System Conﬁguration 10.5.4.2 SIU Interrupt Mask Register (SIMASK) Bits in SIMASK correspond to the interrupt request bits in SIPEND. Setting SIMASK bits enable the generation of interrupt requests to the core. SIMASK is updated by the software, which must determine which interrupt sources are enabled at a given time. Field IRM0 LVM0 IRM1 LVM IRM2 LVM2 IRM3 LVM3 IRM4 LVM4 IRM5 LVM5 IRM6 LVM6 IRM7 LVM7...
Page 286: Siu Interrupt Edge/Level Register (Siel)
1, 3, 5, Wake-up mask 0–7 7, 9, 11, 0 Not allowed to exit from low-power mode. 1 Low-level detection in IRQn allows the MPC850 to exit or wake up from low-power mode. 13, 15 16–31 — Reserved, should be cleared.
Page 287: Siu Interrupt Vector Register (Sivec)
System Conﬁguration 10.5.4.4 SIU Interrupt Vector Register (SIVEC) The SIU interrupt vector register (SIVEC) is shown in Figure 10-13. Field INTC — Reset 0011_1100_0000_0000 Addr (IMMR & 0xFFFF0000) + 0x01C Field — Reset 0000_0000_0000_0000 Addr (IMMR & 0xFFFF0000) + 0x01E Figure 10-13.
Page 288: The Bus Monitor
Control of the bus monitor is provided in the SYPCR. The bus monitor ensures that each bus cycle initiated by the MPC850 terminates within a reasonable time. The MPC850’s bus monitor does not monitor accesses initiated by external masters. At the start of the transfer start signal (TS), the monitor begins counting and stops when transfer acknowledge (TA), retry (RETRY) or transfer error (TEA) is asserted.
Page 289: The Software Watchdog Timer
The Software Watchdog Timer the bus monitor terminates the cycle by internally asserting TEA. The programmability of the timeout allows for a variation in system peripheral response time. The timing mechanism is clocked by the system clock divided by eight. The maximum value is 2,040 system clocks.
Page 290: Software Service Register (Swsr)
Figure 10-17. Software Service Register (SWSR) Table 10-13 describes SWSR ﬁelds. Table 10-13. SWSR Field Descriptions Bits Name Description 0–15 Sequence. This ﬁeld is the pattern that is used to control the state of the software watchdog timer. MPC850 Family User’s Manual...
Page 291: The Powerpc Decrementer
10.8 The PowerPC Decrementer A PowerPC-deﬁned 32-bit decrementing counter supports the decrementer interrupt. In the MPC850, the decrementer is clocked by TMBCLK, so TBSCR[TBE] must be set for the decrementer to start. The timebase and decrementer counters are driven by TMBCLK:...
Page 292: The Powerpc Timebase
10.9 The PowerPC Timebase The PowerPC timebase is a 64-bit free-running binary counter. For the MPC850, the timebase is clocked by TMBCLK. The timebase period is as follows: 2 64...
Page 293: Timebase Register (Tbu And Tbl)
The PowerPC Timebase 10.9.1 Timebase Register (TBU and TBL) The timebase register (TB) holds a 64-bit integer that is incremented periodically. It is implemented in two parts, time base upper and time base lower (TBU and TBL). There is no automatic initialization of TB, therefore, system software must perform this initialization.
Page 294: Timebase Reference Registers (Tbrefa And Tbrefb)
TBSCR is a keyed register. It must be unlocked in TBSCRK before it can be written. Field TBIRQ REFA REFB — REFAE REFBE TBF Reset 0000_0000_0000_0000 Addr (IMMR & 0xFFFF0000) + 0x200 Figure 10-22. Timebase Status and Control Register (TBSCR) MPC850 Family User’s Manual...
Page 295: The Real-Time Clock
The Real-Time Clock Table 10-19 describes TBSCR ﬁelds. Table 10-19. TBSCR Field Descriptions Bits Name Description 0–7 TBIRQ Timebase interrupt request. Determines interrupt priority level of the timebase. To specify a certain level, the appropriate bit should be set. REFA Reference interrupt status.
Page 296: Real-Time Clock Status And Control Register (Rtcsc)
1 Assumes that PITRTCLK is driven by a 38.4-KHz crystal. Seconds interrupt enable. If set, the real-time clock generates an interrupt when SEC is set. Alarm interrupt enable. If set, the real-time clock generates an interrupt when ALR is set. MPC850 Family User’s Manual...
Page 297: Real-Time Clock Alarm Register (Rtcal)
The Real-Time Clock Table 10-20. RTCSC Field Descriptions (Continued) Bits Name Description Real-time clock freeze enable 0 The real-time clock is unaffected by the FRZ signal. 1 The FRZ signal stops the real-time clock. Real-time clock enable. If set, real-time clock timers are enabled. 10.10.2 Real-Time Clock Register (RTC) The 32-bit real-time clock register (RTC) contains the current value of the real-time clock.
Page 298: Real-Time Clock Alarm Seconds Register (Rtsec)
Note that RTSEC is a keyed register. It must be unlocked in RTSECK before it can be written. Field COUNTER — Reset — Addr (IMMR & 0xFFFF0000) + 0x228 Field — Reset — Addr (IMMR & 0xFFFF0000) + 0x22A Figure 10-27. Real-Time Clock Alarm Seconds Register (RTSEC) MPC850 Family User’s Manual...
Page 299: The Periodic Interrupt Timer (Pit)
The Periodic Interrupt Timer (PIT) Table 10-23 describes RTSEC ﬁelds. Table 10-23. RTSEC Field Descriptions Bits Name Description 0–13 COUNTER Counter bits (fraction of a second). Bit 13 is always the lsb of the count. It either resets at 8192 or at 9600, as programmed.
Page 300: Periodic Interrupt Status And Control Register (Piscr)
Periodic interrupt status. Can be cleared by writing a 1 to it (zero has no effect). 0 The PIT is unaffected. 1 The PIT has issued an interrupt. 9–12 — Reserved, should be cleared. Periodic interrupt enable 0 Disables the PS bit. 1 Enables the PS bit to generate an interrupt. MPC850 Family User’s Manual...
Page 301: Pit Count Register (Pitc)
The Periodic Interrupt Timer (PIT) Table 10-24. PISCR Field Descriptions (Continued) Bits Name Description PITF PIT freeze enable 0 The PIT is unaffected by the FRZ signal. 1 The FRZ signal stops the PIT. Periodic timer enable 0 The PIT is disabled. 1 The PIT is enabled.
Page 302: General Siu Timers Operation
The PIT, decrementer, and timebase are not affected by low-power modes and continue to run at their respective frequencies. These timers can generate an interrupt to bring the MPC850 out of the low-power modes. MPC850 Family User’s Manual...
Page 303: Types Of Reset
Includes SIU pin conﬁguration, the parallel I/O conﬁguration and the memory controller conﬁguration Includes all other CPM and core logic not explicitly noted elsewhere in the table 11.1 Types of Reset The MPC850 has several sources of input to the reset logic: • Power-on reset • External hard reset •...
Page 304: Power-On Reset
The hard reset (HRESET) signal is a bidirectional, active low, open-collector I/O signal. The MPC850 can only sample an external assertion of HRESET if it occurs while the MPC850 is not internally asserting HRESET. While HRESET is asserted, SRESET is also asserted.
Page 305: Pll Loss Of Lock
Types of Reset established, and the core stops driving the HRESET and SRESET signals. Following the negation of HRESET and SRESET a 16-cycle period passes before an external hard or soft reset will be sampled. Note that external pull-up resistors should be provided to drive HRESET and SRESET high.
Page 306: Power-On And Hard Reset Sequence
The soft reset (SRESET) signal is also a bidirectional, active low, open-collector I/O signal. The MPC850 can detect an external assertion of SRESET only if it occurs while the MPC850 is not internally asserting HRESET or SRESET.
Page 307: Soft Reset Sequence
11.2 Reset Status Register (RSR) The 32-bit reset status register (RSR) is powered by the keep alive power supply. It is memory-mapped into the MPC850 system interface unit register map and receives its default reset values at power-on reset. Field EHRS ESRS LLRS SWRS CSRS DBHRS DBSRS JTRS —...
Page 308 11.3 MPC850 Reset Conﬁguration When a hard reset event occurs, the MPC850 reconﬁgures both its internal hardware and the development port. A soft reset is used to reconﬁgure the development port without changing the MPC850’s internal machine state. The following sections describe the conﬁguration of the MPC850 using hard and soft reset events.
Page 309: Hard Reset
MPC850 Reset Conﬁguration 11.3.1 Hard Reset When a hard reset event occurs, the MPC850 determines its initial mode of operation by sampling the values present on the data bus (D[0–31]) or from an internal default constant (D[0–31] = 0x00000000). If the RSTCONF signal is asserted at sampling time, the conﬁguration is sampled from the data bus.
Page 310 Figure 11-5. Reset Configuration Sampling for Short PORESET Assertion Figure 11-6 shows a reset operation with a long PORESET signal assertion. CLKOUT PORESET INTPORESET HRESET RSTCONF TSUP D[0:31] Default RSTCONF Controlled Figure 11-6. Reset Configuration Sampling for Long PORESET Assertion MPC850 Family User’s Manual...
Page 311: Hard Reset Configuration Word
MPC850 Reset Conﬁguration Figure 11-7 shows the conﬁguration data sampling timing relative to HRESET and CLKOUT. CLKOUT HRESET Maximum Time of Reset Recognition RSTCONF Data Reset Configuration Word Maximum Setup Time of Reset Recognition Sample Data Sample Data Sample Data...
Page 312 DBPC = 00 DBPC = 01 DBPC = 10 DBPC = 11 ALE_B/DSCK/AT1 Deﬁned by DBGC. Reserved DSCK Note that if DBPC = 11, DBPC IP_B6/DSDI/AT0 DSDI overrides DBGC. OP3/MODCK2/DSDO DSDO IP_B7/PTR/AT3 TCK/DSCK DSCK TDI/DSDI DSDI TDO/DSDO DSDO MPC850 Family User’s Manual...
Page 313: Soft Reset
Reserved. This bit is reserved for future use and should be allowed to ﬂoat. 11.3.2 Soft Reset When a soft reset event occurs, the MPC850 reconﬁgures the development port. See Section 44.3.1.2, “Entering Debug Mode,” and Section 44.3.2.3.3, “Selection of Development Port Clock Mode.”...
Page 314 TRST and Power Mode Considerations MPC850 Family User’s Manual...
Page 315 Part IV The Hardware Interface Intended Audience Part IV is intended for system designers who need to understand how each MPC850 signal works and how those signals interact. Contents Part IV describes external signals, clocking, memory control, and power management of the MPC850.
Page 316 This section lists additional reading that provides background for the information in this manual as well as general information about the PowerPC architecture. MPC8xx Documentation Supporting documentation for the MPC850 can be accessed through the world-wide web at http://www.motorola.com/SPS/RISC/netcomm. This documentation includes technical speciﬁcations, reference materials, and detailed applications notes.
Page 317 Indicates an undeﬁned numerical value ¬ NOT logical operator & AND logical operator OR logical operator Acronyms and Abbreviations Table i contains acronyms and abbreviations used in this document. Note that the meanings for some acronyms (such as SDR1 and DSISR) are historical, and the words for which an acronym stands may not be intuitively obvious.
Page 318 System interface unit Serial management controller Systems network architecture. Serial peripheral interface Special-purpose register SRAM Static random access memory Time-division multiplexed Translation lookaside buffer Time-slot assigner Transmit UART Universal asynchronous receiver/transmitter UISA User instruction set architecture MPC850 Family User’s Manual...
Page 319 Table v. Acronyms and Abbreviated Terms (Continued) Term Meaning User-programmable machine USART Universal synchronous/asynchronous receiver/transmitter Part IV. The Hardware Interface.
Page 320 MPC850 Family User’s Manual...
Page 321 Chapter 12 External Signals This chapter contains descriptions of the MPC850 family input and output signals, showing multiplexing, pin assignments, and reset values. NOTE: These signals speciﬁcally refer to the MPC850DE, the superset of the basic MPC850 device; see Appendix F for implementation of the actual MPC850 device.
Page 322 PD[3] <> 1 1 <> IP_B5/LWP1/VF1 > 1 1 <> IP_B6/DSDI/AT0 TDI/DSDI > 1 1 <> IP_B7/PTR/AT3 TCK/DSCK > 1 1 <> OP2/MODCK1/STS TRST > 1 1 <> OP3/MODCK2/DSDO TDO/DSDO < 1 Figure 12-1. MPC850 Signals Group MPC850 Family User’s Manual...
Page 323 PD[11] < PD[10] < PD[9] < PD[8] <> PD[7] <> PD[6] <> PD[5] <> PD[4] <> PD[3] <> > TDI/DSDI > TCK/DSCK > TRST > TDO/DSDO < Figure 12-2. MPC850 Signals and Pin Numbers (Part 1) Chapter 12. External Signals...
Page 324 > TEXP D31—E3 <> ALE_B/DSCK/AT1 < WAIT_B A8, C8 <> IP_B(0:1)/IWP(0:1)/VFLS(0:1) <> IP_B2/IOIS16_B/AT2 <> IP_B3/IWP2/VF2 <> IP_B4/LWP0/VF0 <> IP_B5/LWP1/VF1 <> IP_B6/DSDI/AT0 <> IP_B7/PTR/AT3 <> OP2/MODCK1/STS <> OP3/MODCK2/DSDO Figure 12-3. MPC850 Signals and Pin Numbers (Part 2) MPC850 Family User’s Manual...
Page 325: System Bus Signals
System Bus Signals 12.1 System Bus Signals The MPC850 system bus consists of all signals that interface with the external bus. Many of these signals perform different functions, depending on how the user assigns them. The input and output signals, described in Table 12-1, are identiﬁed by their abbreviation. Note that the pin numbering shown is Motorola proprietary (non-JEDEC).
Page 326 Data Bus—Provides the general-purpose data path between Figure 12-3. Three-state the MPC850 and all other devices. The 32-bit data path can be dynamically sized to support 8-, 16-, or 32-bit transfers. D0 is the msb of the data bus. MPC850 Family User’s Manual...
Page 327 Data Parity 0—Provides parity generation and checking for IRQ3 Three-state D[0–7] for transfers to a slave device initiated by the MPC850. The parity function can be deﬁned independently for each one of the addressed memory banks (if controlled by the memory controller) and for the rest of the slaves sitting on the external bus.
Page 328 Hi-Z Bidirectional Bus Grant—Asserted when the arbiter of the external bus grants the bus to a speciﬁc device. When the MPC850 is conﬁgured to work with the internal arbiter, BG is conﬁgured as an output and asserted every time the external master asserts BR and its priority request is higher than any internal sources requiring a bus transfer.
Page 329 BS_AB0 external slave controlled by the GPCM is initiated by the IORD MPC850. WE0 is asserted if D[0–7] contains valid data to be stored by the slave device. Byte Select 0 on UPMA or UPMB—Output asserted under control of the UPMA or UPMB, as programmed by the user. In a read or write transfer, the line is only asserted if D[0–7]...
Page 330 Address Strobe—AS is driven by an external asynchronous master to indicate a valid address on the A[6:31] lines. The memory controller in the MPC850 will synchronize this signal and access the memory device addressed if it is recognized to be under its control.
Page 331 Address Latch Enable B—This output is asserted when the DSCK Section Three-state MPC850 initiates an access to a region under the control of 12.5 the PCMCIA socket B interface. Development Serial Clock—This input is the clock for the debug port interface.
Page 332 Name Reset Number Type Description IP_B3 Bidirectional Input Port B 3—The MPC850 monitors this input; its value IWP2 Section and changes are reported in the PIPR and PSCR of the 12.5 PCMCIA interface. Instruction Watchpoint 2—This output reports the detection of an instruction watchpoint in the program ﬂow executed by the...
Page 333 Reset Number Type Description Hi-Z Bidirectional Output Port 2—This output is generated by the MPC850 as a MODCK1 result of a write to the PGCRB register in the PCMCIA interface. Mode Clock 1—Input sampled when PORESET is negated to conﬁgure PLL/clock mode.
Page 334 General-Purpose I/O Port B Bit 28—Bit 28 of the SPIMISO (Optional: general-purpose I/O port B. BRGO3 Open-drain) SPIMISO—SPI input data when the MPC850 is a master; SPI output data when it is a slave. BRGO3—BRG3 output clock. PB[27] Hi-Z Bidirectional General-Purpose I/O Port B Bit 27—Bit 27 of the...
Page 335 System Bus Signals Table 12-1. Signal Descriptions (Continued) Name Reset Number Type Description PB[23] Hi-Z Bidirectional General-Purpose I/O Port B Bit 23—Bit 23 of the SMSYN1 (Optional: general-purpose I/O port B. SDACK1 Open-drain) SMSYN1—SMC1 external sync input. SDACK1—SDMA acknowledge 1 output that is used as a peripheral interface signal for IDMA emulation.
Page 336 I/O port D. PD[13] Hi-Z Bidirectional General-Purpose I/O Port D Bit 13—Bit 13 of the general-purpose I/O port D. PD[12] Hi-Z Bidirectional General-Purpose I/O Port D Bit 12—Bit 12 of the general-purpose I/O port D. MPC850 Family User’s Manual...
Page 337 System Bus Signals Table 12-1. Signal Descriptions (Continued) Name Reset Number Type Description PD[11] Hi-Z Bidirectional General-Purpose I/O Port D Bit 11—Bit 11 of the general-purpose I/O port D. PD[10] Hi-Z Bidirectional General-Purpose I/O Port D Bit 10—Bit 10 of the general-purpose I/O port D.
Page 338: Active Pull-Up Buffers
Further, external logic must not attempt to drive these signals low while active pull-up buffers are enabled as outputs, because the buffers will reactivate and drive high, resulting in a buffer ﬁght and possible damage to the MPC850, to the system, or to both.
Page 339: Internal Pull-Up And Pull-Down Resistors
When the MPC850’s memory controller responds to the access on the external bus, then: • For chip selects controlled by a GPCM set for external TA, the MPC850’s TA buffer is not enabled as an output. • For chip-selects controlled by the GPCM set to terminate in n wait-states, TA is enabled as an output on cycle (n-1) and driven high, then is driven low on cycle n, terminating the bus transaction.
Page 340: Recommended Basic Pin Connections
MODCK[1–2] must be used to determine the default clocking mode for the MPC850. After power-on reset, the MODCK[1–2] pins change function and become outputs. Thus, if these alternate functions are also desired, then the MODCK[1–2] conﬁguration should be set...
Page 341: Jtag And Debug Ports
12.4.4 Unused Outputs Unused outputs can be left unterminated. 12.5 Signal States during Hardware Reset During hardware reset (HRESET or PORESET), the signals of the MPC850 behave as follows: • The bus signals are high-impedance. • The port I/O signals are conﬁgured as inputs, and are therefore high-impedance.
Page 342 ALE_B: low DSCK/AT1: high impedance IP_B[0–1]/IWP[0–1]/VFLS[0–1] IP_B[0–1]: high impedance. IWP[0–1]: high VFLS[0–1]: low IP_B3/IWP2/VF2 IP_B3: high impedance IWP2: high VF2: low IP_B4/LWP0/VF0 IP_B4: high impedance LWP0: high VF0: low IP_B5/LWP1/VF1 IP_B5: high impedance LWP1: high; VF1: low MPC850 Family User’s Manual...
Page 343: Bus Transfer Overview
Chapter 13 External Bus Interface The MPC850 bus is a synchronous, burstable bus that can support multiple masters. Signals driven on this bus are required to make the setup and hold time relative to the bus clock’s rising edge. The MPC850 architecture supports byte, half-word, and word operands allowing access to 8-, 16-, and 32-bit data ports through the use of synchronous cycles controlled by the size outputs (TSIZ0, TSIZ1).
Page 344: Bus Interface Signal Descriptions
Bus Interface Signal Descriptions The MPC850’s address bus speciﬁes the address for the transfer and its data bus transfers the data. Control signals indicate the beginning of the cycle and the type of cycle, as well as the address space and size of the transfer. The selected device controls cycle length with signal(s) used to terminate the cycle.
Page 345 RD/WR Driven by the MPC850 along with the address when it owns the external bus. Read/Write Driven high indicates that a read access is in progress. Driven low indicates that a write access is in progress.
Page 346 Indicates additional information about the address on the current transaction. Trace BDIP Driven by the MPC850 when it owns the external bus as part of the burst protocol. Burst Data in Asserted indicates that the second beat in front of the current one is requested by Progress the master.
Page 347 D[16–23]DP2 D[24–31]DP3 Driven by the MPC850 when it is external bus master and it initiated a write transaction to a slave device. Each line has the parity value (even or odd) of its corresponding data bus byte. For single-beat transfers, byte lanes not selected by A[30–31] and TSIZ[0–1] will not have a valid parity line.
Page 348: Bus Operations
The MPC850 generates a system clock output (CLKOUT), which directly sets the bus interface operation frequency. Internally, the MPC850 uses a phase-lock loop (PLL) circuit to generate a master clock for all core circuitry (including the bus interface), which is phase-locked to CLKOUT.
Page 349: Single-Beat Read Flow
Bus Operations 13.4.2.1 Single-Beat Read Flow The basic read cycle begins with a bus arbitration, followed by the address transfer, then the data transfer. The following ﬂow and timing diagrams show the handshakes applicable to the ﬁxed transaction protocol. MASTER SLAVE Bus Request (BR) Receives Bus Grant (BG) from arbiter...
Page 350 Bus Operations CLKOUT Receive BG and BB negated Assert BB, drive address and assert TS A[6–31] TSIZ[0–1], AT[0–3] BURST Data Data is Valid Figure 13-5. Basic Timing: Single-Beat Read Cycle, Zero Wait States MPC850 Family User’s Manual...
Page 351 Bus Operations CLKOUT Receive BG and BB negated Assert BB, drive address and assert TS A[6–31] TSIZ[0–1], AT[0–3] BURST Data Wait State Data is Valid Figure 13-6. Basic Timing: Single-Beat Read Cycle, One Wait State Chapter 13. External Bus Interface...
Page 352: Single-Beat Write Flow
Asserts Bus Busy (BB) if no other master is driving Asserts Transfer Start (TS) Drives address and attributes Drives data Asserts Transfer Acknowledge (TA) Interrupts data driving Figure 13-7. Basic Flow of a Single-Beat Write Cycle MPC850 Family User’s Manual...
Page 353 Bus Operations CLKOUT Receive BG and BB negated Assert BB, drive address and assert TS A[6–31] TSIZ[0–1], AT[0–3] BURST Data Data is sampled Figure 13-8. Basic Timing: Single-Beat Write Cycle, Zero Wait States Chapter 13. External Bus Interface...
Page 354 The general case of single-beat transfers assumes that external memory has a 32-bit port size. The MPC850 provides an effective mechanism for interfacing with 16- and 8-bit port size memories by allowing transfers to these devices when they are controlled by the internal memory controller.
Page 355: Burst Transfers
A28 and A29 (and A30 in the case of a 16-bit port size slave device) of the supplied address for each transfer, causing the address to wrap around at the end of the four-word block. For slaves controlled by the memory controller, the MPC850 increments the address on A[28–31].
Page 356: Burst Operations
ﬁrst word of the asserts the burst-inhibit signal (BI) with TA for the ﬁrst transfer of the burst access. The MPC850 responds by terminating the burst and accessing the rest of the 16-byte block, using three read/write cycles (each one for a word) for a 32-bit port-width slave, seven read/write cycles for a 16-bit port-width slave, or ﬁfteen read/write...
Page 357 8 bits and controlled by the internal memory controller, the burst includes 16 beats. The MPC850 bus supports critical data ﬁrst access for ﬁxed-size burst. The order of wraparound wraps back to the critical data. For example, assuming data 2 is critical: •...
Page 358 Asserts Transfer Acknowledge (TA) Receives Data BDIP asserted Negates Burst Data in Progress (BDIP) Don’t drive data Returns data Asserts Transfer Acknowledge (TA) Receives data BDIP asserted Don’t drive data Figure 13-11. Basic Flow of a Burst-Read Cycle MPC850 Family User’s Manual...
Page 359 Bus Operations CLKOUT A[6–31], AT[0–3] TSIZ[0–1] BURST Last Beat Expects Another Data BDIP Data Data is Data is Data is Data is Valid Valid Valid Valid Figure 13-12. Burst-Read Cycle: 32-Bit Port Size, Zero Wait State Chapter 13. External Bus Interface...
Page 360 CLKOUT A[6–31], AT[0–3] TSIZ[0–1] BURST Last Beat Expects Another Data BDIP Data Data is Data is Data is Data is Valid Valid Valid Valid Wait State Figure 13-13. Burst-Read Cycle: 32-Bit Port Size, One Wait State MPC850 Family User’s Manual...
Page 361 Bus Operations CLKOUT A[6–31], AT[0–3] TSIZ[0–1] BURST Last Beat Expects Another Data BDIP Data Data is Data is Data is Data is Valid Valid Valid Valid Wait State Figure 13-14. Burst-Read Cycle: 32-Bit Port Size, Wait States between Beats Chapter 13. External Bus Interface...
Page 362 Bus Operations CLKOUT A[6–31], AT[0–3] TSIZ[0–1] BURST BDIP Data Figure 13-15. Burst-Read Cycle: 16-Bit Port Size, One Wait State between Beats MPC850 Family User’s Manual...
Page 363 Bus Operations MASTER SLAVE Bus Request (BR) Receives Bus Grant (BG) from arbiter Asserts Bus Busy (BB) if no other master is driving Asserts Transfer Start (TS) Drives address and attributes Drives BURST asserted Receives address Drives data Asserts burst data in progress (BDIP) Asserts Transfer Acknowledge (TA) Drives data BDIP asserted...
Page 364 Figure 13-18 shows an attempted burst read to a slave device that does not support bursting. The slave acknowledges the ﬁrst transfer and also asserts the burst-inhibit signal (BI). The MPC850 responds by terminating the burst and accessing the rest of the 16-byte block, using three single-beat read cycles.
Page 365: Alignment And Data Packing On Transfers
Data Figure 13-18. Burst-Inhibit Cycle: 32-Bit Port Size 13.4.5 Alignment and Data Packing on Transfers The MPC850 external bus supports only natural address alignment: • Byte access can have any address alignment. • Half-word access must have A[31] = 0b0.
Page 366 ﬁxed. A 32-bit port must reside on D[0–31], a 16-bit port must reside on D[0–15], and an 8-bit port must reside on D[0–7]. The MPC850 always tries to transfer the maximum amount of data on all bus cycles; for a word operation, it always assumes that the port is 32 bits wide when beginning the cycle.
Page 367 Bus Operations Interface Output Register D[0–7] D[8–15] D[16–23] D[24–31] 32-Bit Port Size 16-Bit Port Size 8-Bit Port Size Figure 13-20. Interface to Different Port Size Devices Table 13-2 lists the bytes required on the data bus for read cycles. Table 13-2. Data Bus Requirements for Read Cycles Address 32-Bit Port 16-Bit Port...
Page 368: Arbitration Phase
— denotes a byte not required during that read cycle. 13.4.6 Arbitration Phase The external bus design provides for a single bus master at any one time, either the MPC850 or an external device. The arbitration of external bus devices contending for bus mastership may be handled either by an external central bus arbiter or by the internal on-chip arbiter.
Page 369: Bus Request (Br)
BR as long as needed. When conﬁgured for external arbitration, the MPC850 drives BR when it requires bus mastership. When the internal on-chip arbiter is used, BR is an input to the internal arbiter and should be driven by the external bus master.
Page 370: Bus Busy (Bb)
See Figure 13-22. External Bus Master MPC850 Slave 2 Figure 13-22. Bus Busy (BB) and Transfer Start (TS) Connection Example Figure 13-23 shows an example bus arbitration between two contending masters. MPC850 Family User’s Manual...
Page 371 Figure 13-23. Bus Arbitration Timing Diagram The MPC850 can be conﬁgured at system reset to use the internal bus arbiter. In this case, the MPC850 is parked on the bus. Section 10.4.2, “SIU Module Conﬁguration Register (SIUMCR),” describes prioritization of external devices relative to the internal MPC850 bus masters.
Page 372: External Bus Parking
13.4.6.4 External Bus Parking During external arbitration, the MPC850 supports bus parking. If the MPC850 detects that an external arbiter has asserted BG to it and BB is negated, the MPC850 starts a transfer without asserting BR. 13.4.7 Address Transfer Phase-Related Signals The following sections describe the address transfer phase-related signals.
Page 373: Address Bus
Bus Operations 13.4.7.2 Address Bus The 26-bit address bus, A[6–31], is byte addressable, so each address can address one or more bytes. A[6] is the msb. The address and its attributes are driven on the bus with TS; they remain valid until the bus master receives a transfer acknowledge from the slave. To distinguish an individual byte, the slave device must observe the TSIZ signals.
Page 374 Core-initiated, normal data, supervisor mode Core-initiated, normal instruction, program trace, user mode Core-initiated, normal instruction, user mode Core-initiated, reservation data, user mode Core-initiated, normal data, user mode DMA-initiated, normal, AT[1–3] user-programmable (see IDMA and DMA function code registers) MPC850 Family User’s Manual...
Page 375 Bus Operations Table 13-5. Address Types Definition (Continued) Core/ User/ Reservation/ Program Instruction/ Reservation Address Space STS TS Supervisor Program Trace Data (AT2) (RSV) Deﬁnitions (AT0) (AT1) Trace (AT3) (PTR) Core-initiated, show cycle address instruction, program trace, supervisor mode Core-initiated, show cycle address instruction, supervisor mode Core-initiated, reservation...
Page 376: Burst Data In Progress (Bdip)
The master asserts BDIP to indicate to the slave that another data beat follows the current data beat. 13.4.8 Termination Signals The following sections discuss the termination signals supported by the MPC850. 13.4.8.1 Transfer Acknowledge (TA) TA indicates normal completion of the bus transfer. The slave asserts TA with every data beat returned or accepted during a burst cycle.
Page 377: Memory Reservation
Figure 13-26. Termination Signals Protocol Timing Diagram 13.4.9 Memory Reservation The MPC850 memory reservation protocol supports multilevel bus structures. For each local bus, reservations are handled by the local reservation logic. The protocol tries to optimize reservation cancellation such that a PowerPC processor is notiﬁed of memory...
Page 378: Kill Reservation (Kr)
Note that for burst transactions, KR should be asserted externally only on the ﬁrst or last beats. Assertion of KR on an intermediate beat may result in erratic operation, including lockup of the MPC850 requiring hard reset. Figure 13-27 shows the reservation protocol for a multi-level (local) bus. The system describes a situation in which the reserved location is in the remote bus.
Page 379: Bus Exception Control Cycles
13.4.10 Bus Exception Control Cycles The MPC850 bus architecture requires assertion of the TA from an external device to signal that the bus cycle is complete. TA is not asserted in the following cases: • The external device does not respond •...
Page 380: Retry
Normal arbitration resumes in the next clock cycle. If the external master does not use the bus, the MPC850 initiates a new transfer with the same address and attributes as before. In Figure 13-29 the same situation is shown where the MPC850 is working with an external arbiter.
Page 381 RETRY Figure 13-29. Retry Transfer Timing–External Arbiter When the MPC850 initiates a burst access, the bus interface only recognizes the RETRY assertion as a retry termination if it detects it before the slave device acknowledges the ﬁrst data beat. Note that for burst transactions, RETRY should be asserted externally only on the ﬁrst or last beats.
Page 382 If a burst access is acknowledged on its ﬁrst beat with a normal TA, but with BI asserted, the following single-beat transfers initiated by the MPC850 to complete the 16 byte transfers process the RETRY signal assertion as a TEA. If the MPC850MPC850 initiates non-burst access to a small port size device, the transfer size of the access is bigger than the slave port size, and the ﬁrst transfer of this access is terminated normally by the assertion...
Page 383 Bus Operations Table 13-6 summarizes how the MPC850 recognizes the termination signals provided by the slave device that is addressed by the initiated transfer. Table 13-6. Termination Signals Protocol RETRY/KR Action Transfer error termination Normal transfer termination Retry transfer termination/kill reservation...
Page 384 Bus Operations MPC850 Family User’s Manual...
Page 385: Features
Figure 14-1 illustrates internal clock source and distribution that includes the system phase-locked loop (SPLL), clock dividers, drivers, and crystal oscillator. 14.1 Features The main features of the MPC850 clocks and power control system are as follows: • Contains system PLL (SPLL) • Supports crystal oscillator circuits •...
Page 386: The Clock Module
Note that only CLKOUT is an actual external output; all other outputs are internal signals. Figure 14-1. Clock Source and Distribution 14.2 The Clock Module The clock module consists of two external reference sources and a programmable phase-locked loop, arranged as shown in Figure 14-2. MPC850 Family User’s Manual...
Page 387: External Reference Clocks
Figure 14-2. Clock Module Components 14.2.1 External Reference Clocks The MPC850 has two input clock sources, provided at the EXTCLK pin or at the EXTAL and XTAL pins. These two clock sources can select to drive three internal clock signals, referred to as OSCCLK, PITRTCLK, and TMBCLK.
Page 388: Off-Chip Oscillator Input (Extclk)
3. The minimum operating frequency of the SPLL, which is 15 MHz 14.2.1.2 Crystal Oscillator Support (EXTAL and XTAL) The MPC850 provides support for crystal oscillator circuits with the oscillator module (OSCM). The OSCM has two different modes, supporting two different ranges of frequencies: 30–50 kHz (referred to as 32 kHz mode) or 3-5 MHz (referred to as 4 MHz...
Page 389: System Pll
14.2.2 System PLL The programmable phase-locked loop, called the system phase-locked loop (SPLL) in the MPC850, generates the overall system operating frequency in integer multiples of the input clock frequency. The SPLL reference clock (OSCCLK) can be generated from either of the external clock sources described in Section 14.2.1, “External Reference Clocks.”...
Page 390 OSCCLK (SPLL input) is OSCM freq [referred to as 32 kHz mode] OSCCLK (SPLL input) is OSCM freq [referred to as 4 MHz mode] OSCCLK (SPLL input) is EXTCLK freq OSCCLK (SPLL input) is EXTCLK freq MPC850 Family User’s Manual...
Page 391: Spll Output Characteristics And Stability
The minimum frequency at which the SPLL is guaranteed to operate is 15 MHz; therefore, the MPC850 must be conﬁgured so that at all times (both after initial system reset and at the ﬁnal operating frequency) the minimum frequency of CLKOUT is 15 MHz. The maximum frequency at which the SPLL is guaranteed to operate is the maximum rated frequency of the part (for example, 50 MHz for a 50-MHz part).
Page 392: Disabling The Spll
Note that because the skew elimination provided by the SPLL is also disabled, this mode of operation invalidates the timing of the MPC850. Thus, this mode must not be used as a normal operating mode; its only valid use is for low-frequency testing of board integrity during production.
Page 393: Clocks Derived From The Spll Output
ﬁxed frequency and the memory refresh to continue at a uniform rate even when the rest of the MPC850 is operating at a reduced frequency (for example, when in normal low or doze low modes)
Page 394: The Internal General System Clocks (Gclk1C, Gclk2C Gclk1, Gclk2)
• The GCLKx clocks are supplied to the SIU, clock module, memory controller, and most of the other blocks in the CPM. They are not active when the MPC850 is in sleep or deep-sleep modes. GCLKx can be dynamically switched between two different frequencies determined by dividers programmed in SCCR[DFNH] and SCCR[DFNL], as shown in Figure 14-6.
Page 395: Memory Controller And External Bus Clocks (Gclk1_50 Gclk2_50, Clkout)
14.3.1.2 Memory Controller and External Bus Clocks (GCLK1_50, GCLK2_50, CLKOUT) The MPC850 provides the capability to run the external bus and memory controller at a lower frequency than the internal modules. This capability is provided by the external bus frequency dividers. The external bus clocks GCLK1_50 and GCLK2_50 are derived from GCLK1 and GCLK2, as determined by the SCCR[EBDF].
Page 396 The low-power frequency dividers described in Section 14.3.1.1, “The Internal General System Clocks (GCLK1C, GCLK2C, GCLK1, GCLK2)” also effect the frequency and duty cycle of GCLK1_50, GCLK2_50, and CLKOUT. For an example of this, see Figure 14-9. MPC850 Family User’s Manual...
Page 397 Clock Signals GCLK1 GCLK2 GCLK1_50 (EBDF=00) GCLK2_50 (EBDF=00) CLKOUT (EBDF=00) GCLK1_50 (EBDF=01) GCLK2_50 (EBDF=01) CLKOUT (EBDF=01) Figure 14-9. Memory Controller and External Bus Clocks Timing Diagram for (CSRC=0 and DFNH=1) or (CSRC=1 and DFNL=0) The frequency of GCLK1_50 and GCLK2_50 are effected both by the SCCR[DFNH] and SCCR[DFNL] dividers and by the SCCR[EBDF] divider.
Page 398: Clkout Special Considerations: 1:2:1 Mode
To enable synchronization of a system to the EXTCLK signal while still allowing the internal circuits of the MPC850 to operate at an increased frequency, it is necessary to maintain synchronization of the EXTCLK and CLKOUT signal. Speciﬁcally, this operation entails: •...
Page 399: The Pit And Rtc Clock (Pitrtclk)
SYNCCLK allows the serial interface, serial communication controller, and serial management controllers to continue operating at a ﬁxed frequency, even when the rest of the MPC850 is operating at a reduced frequency.
Page 400: The Time Base And Decrementer Clock (Tmbclk)
OSCCLK 14.4 Power Distribution The various modules of the MPC850 are connected to four distinct power rails. These power rails have different requirements, as explained in the following sections. The organization of the power rails is shown in Figure 14-12.
Page 401: I/O Buffer Power (Vddh)
Digital SPLL V DDH V DDL V DDSYN Figure 14-12. MPC850 Power Rails A complete tabulation of modules and power supplies is given in Table 14-6. Table 14-6. MPC850 Modules vs. Power Rails Block VDDH VDDL VDDSYN KAPWR I/O Pad...
Page 402: Internal Logic Power (Vddl)
14.5 Power Control (Low-Power Modes) To optimize power consumption, the MPC850 provides low-power modes that can be used to dynamically activate and deactivate certain internal modules, such that only the needed modules are operating at any given time. In addition to normal high mode (i.e. fully activated), the MPC850 supports normal low, doze high, doze low, sleep, deep-sleep, and power-down modes.
Page 403 These events are enabled in the SCCR[PRQEN]. The characteristics of each low-power mode are summarized in Table 14-7. Table 14-7 also provides equations for approximate power consumption equations for each of these modes. Table 14-7. MPC850 Low-Power Modes Typical Return Time from...
Page 404 Software is active only in normal high/low modes. Software initiation of power-down mode requires that the TEXP output be used by external logic to gate main power (VDDH, VDDL, and VDDSYN). Figure 14-13. MPC850 Low-Power Mode Flowchart MPC850 Family User’s Manual...
Page 405: Normal High Mode
Power Control (Low-Power Modes) 14.5.1 Normal High Mode Normal high mode is the default mode of the MPC850. In this mode, the GCLKx frequency is determined by SCCR[DFNH], and all modules of the MPC850 are enabled. For more information about SCCR[DFNH], refer to Section 14.3.1.1, “The Internal General System Clocks (GCLK1C, GCLK2C, GCLK1, GCLK2).
Page 406: Doze Low Mode
Section 14.5.8, “TMIST: Facilitating Nesting of SIU Timer Interrupts.” The MPC850 has the option to temporarily leave doze low mode and enter doze high mode when CPM activity occurs. This option is enabled in SCCR[CRQEN]. When the CP ﬁnishes servicing the peripheral request, the MPC850 automatically reenters doze low...
Page 407: Sleep Mode
Power Control (Low-Power Modes) Upon resumption of processing in normal high or low mode, the MPC850 jumps to the external interrupt vector to process the interrupt source. When the core returns from the exception handler via rﬁ , it resumes processing from the instruction following that which initiated entry into doze mode.
Page 408: Power-Down Mode
14.5.7.1 Software Initiation of Power-Down Mode, with Automatic Wake-up Power-down mode can be initiated in software if the external TEXP signal is used to control the power supply for VDDH, VDDL, and VDDSYN. If software clears TEXPS, the TEXP MPC850 Family User’s Manual...
Page 409 Figure 14-14. The MPC850 should then go through a normal hard reset sequence. When performing this hard reset sequence, it is important to allow enough time for the oscillator to warm up and the SPLL to lock.
Page 410: Maintaining The Real-Time Clock (Rtc) During Shutdown Or Power Failure
MPC850. If power dips below the threshold, PORESET is driven to the MPC850, which resets all of the modules of the MPC850 except the RTC. If power fails entirely, PORESET remains asserted, but the RTC continues to operate if a backup power supply (battery) is connected to KAPWR.
Page 411: Tmist: Facilitating Nesting Of Siu Timer Interrupts
14.6.1 System Clock and Reset Control Register (SCCR) The SPLL has a 32-bit control register that is powered by keep-alive power. The system clock and reset control register (SCCR), shown in Figure 14-15, is memory-mapped into the MPC850 SIU’s register map. Field —...
Page 412 This ﬁeld is initialized during hard reset using the hard reset conﬁguration word in Section 11.3.1.1, “Hard Reset Conﬁguration Word.” 00 CLKOUT is GCLK2 divided by 1. 01 CLKOUT is GCLK2 divided by 2. 1x Reserved. 15–16 — Reserved, should be cleared. MPC850 Family User’s Manual...
Page 413: Pll, Low-Power, And Reset Control Register (Plprcr)
Division factor high frequency. Sets the VCOOUT frequency division factor for general system clocks to be used in normal mode. In normal mode, the MPC850 automatically switches to the DFNH frequency. To select the DFNH frequency, load this ﬁeld with the divide value and clear CSRC.
Page 414 When in power-down mode (LPM=11), the TEXPS bit also controls the TEXP external signal as shown below. See Section 14.5.7.1, “Software Initiation of Power-Down Mode, with Automatic Wake-up.” 0 TEXP is negated. 1 TEXP is asserted. — Reserved, should be cleared. MPC850 Family User’s Manual...
Page 415 Clock and Power Control Registers Table 14-9. PLPRCR Field Descriptions (Continued) Bits Name Description TMIST Timers interrupt status. Cleared at reset. Set when a real-time clock, periodic interrupt timer, timebase, or decrementer interrupt occurs. This bit is cleared by writing a 1; writing a zero has no effect.
Page 416 Clock and Power Control Registers MPC850 Family User’s Manual...
Page 417: Features
Chapter 15 Memory Controller The memory controller is responsible for controlling a maximum of eight memory banks shared between a general-purpose chip-select machine (GPCM) and a pair of sophisticated user-programmable machines (UPMs). It supports a glueless interface to SRAM, EPROM, ﬂash EPROM, regular DRAM devices, self-refresh DRAMs, extended data output DRAM devices, synchronous DRAMs, and other peripherals.
Page 418 — Internal address multiplexing for all on-chip bus masters supporting 64-, 128-, 256-, and 512-Kbyte, and 1-, 2-, 4-, 8-, 16-, 32-, 64-, 128-, 256-Mbyte page banks — Glueless interface to EDO, self refresh, and synchronous DRAM devices MPC850 Family User’s Manual...
Page 419 Features Figure 15-1 is a block diagram of the memory controller. Address [0–16], AT[0–2] Address Latch Multiplexer Incrementer Base Register (BR) Base Register (BR) NA and AMX Fields in RAM Word Option Register (OR) Option Register (OR) Attributes SCY[0–3] CS[0–7] Expired WE[0–3] Wait State...
Page 420: Basic Architecture
• The full 32-bit decode is available internally, even if all 32 bits are not visible outside of the MPC850. For external master transactions, the memory controller extends the 26-bit external address line to 32 bits and the 6 msbs are zeros.
Page 421: System Configuration
(AT[0–2]). For additional ﬂexibility, address-type comparisons provide a mask option. The memory controller functionality minimizes the need for glue logic in MPC850-based systems. In Figure 15-3, CS0 is used with the 16-bit boot EPROM with BR0[MS] defaulting to select the GPCM.
Page 422: Chip-Select Programming Common To The Gpcm And Upm
Option register bank 0–7 register (ORx) √ √ Memory status register (MSTAT) √ √ Memory command register (MCR) √ Machine A mode register (MAMR) √ Machine B mode register (MBMR) √ Memory data register (MDR) √ MPC850 Family User’s Manual...
Page 423: Address Space Programming
Chip-Select Programming Common to the GPCM and UPM Table 15-1. Memory Controller Register Usage (Continued) Register Used by the GPCM Used by a UPM Memory address register (MAR) √ Memory periodic timer prescaler register (MPTPR) √ 15.3.1 Address Space Programming Each bank has an option register (ORx) and a base register (BRx), which contains a V bit that indicates that the information for the chip-select is valid.
Page 424: Memory Bank Protection Status
The memory periodic timer prescaler register (MPTPR) deﬁnes the divisor of the external bus clock used as the memory periodic timer input. 15.3.9 GPCM-Speciﬁc Registers There are no GPCM-speciﬁc registers. All GPCM characteristics are deﬁned in the subﬁelds of individual BRx and ORx registers. MPC850 Family User’s Manual...
Page 425: Register Descriptions
Register Descriptions 15.4 Register Descriptions The following sections describe the registers used by the memory controller. 15.4.1 Base Registers (BRx) The base registers (BR0–BR7) contain the base address and address types that the memory controller uses to compare the value on the address bus with the current address accessed. It also includes a memory attribute and selects the machine for memory operation handling.
Page 426: Option Registers (Orx)
1 This bank is valid. The CS signal does not assert until V is set. 15.4.2 Option Registers (ORx) The option registers (OR0–OR7), shown in Figure 15-7, contain the address and address type mask bit for address bus comparison. It also includes all GPCM parameters. MPC850 Family User’s Manual...
Page 427 Register Descriptions 10 11 Field Reset 0000_0000_0000_0000 Addr (IMMR & FFFF0000) + 0x104 (OR0), 0x10C (OR1), 0x114 (OR2), 0x11C (OR3), 0x124 (OR4), 0x12C (OR5), 0x134 (OR6), 0x13C (OR7) 17 18 19 24 25 26 27 Field CSNT/SAM ACS/G5LA,G5LS BIH SETA TRLX EHTR —...
Page 428 Select external transfer acknowledge (GPCM only). 0 Internal or external transfer acknowledge can acknowledge this access, whichever comes ﬁrst. 1 The memory controller does not generate TA for this bank; instead the peripheral must generate it on the external TA signal. MPC850 Family User’s Manual...
Page 429: Memory Status Register (Mstat)
Register Descriptions Table 15-4. ORx Field Descriptions (Continued) Bits Name Description TRLX Timing relaxed (GPCM only) 0 Timing is not relaxed. 1 In addition to the timing parameters programmed in other ORx ﬁelds, timing is further relaxed. See the effect of TRLX in Table 15-11. TRLX also doubles the wait-states programmed in SCY. EHTR Extended hold time on read.
Page 430: Machine A Mode Register/Machine B Mode Registers (Mxmr)
(see Table 15-18). The SAM bit enables address multiplexing in the ﬁrst clock cycle. The AMx ﬁeld of the RAM array entry enables address multiplexing in subsequent clock cycles. (see Table 15-19). — Reserved, should be cleared. MPC850 Family User’s Manual...
Page 431: Memory Command Register (Mcr)
Register Descriptions Table 15-6. MxMR Field Descriptions (Continued) Bits Name Description 13–14 Disable timer period. Guarantees a minimum time between accesses to the same memory bank if it is controlled by the UPMx. This function can be used to guarantee a minimum RAS precharge time.
Page 432: Memory Data Register (Mdr)
15.4.6 Memory Data Register (MDR) The memory data register (MDR) contains data written to or read from the RAM array for commands. MDR must be set up before issuing a command to READ WRITE WRITE the MCR. MPC850 Family User’s Manual...
Page 433: Memory Address Register (Mar)
Register Descriptions Field Reset 0000_0000_0000_0000 Address (IMMR & FFFF0000) + 0x17C Field Reset 0000_0000_0000_0000 Address (IMMR & FFFF0000) + 0x17E Figure 15-12. Memory Data Register (MDR) Table 15-8 describes MDR. Table 15-8. MDR Field Descriptions Bits Name Description 0–31 Memory data. Contains the RAM array word. 15.4.7 Memory Address Register (MAR) The memory address register contains an address to be driven on the external bus in the case of a...
Page 434: Memory Periodic Timer Prescaler Register (Mptpr)
— Reserved, should be cleared. 15.5 General-Purpose Chip-Select Machine (GPCM) The GPCM allows a glueless and ﬂexible interface between the MPC850, SRAM, EPROM, FEPROM, ROM devices, and external peripherals. The GPCM contains three basic conﬁguration register groups—BRx, ORx, and MSTAT.
Page 435 General-Purpose Chip-Select Machine (GPCM) MPC850 32-Bit Wide SRAM 128K WE[0–3] WE[0–3] GPL_x1/OE A[15–29] Address D[0–31] Data Figure 15-15. GPCM-to-SRAM Conﬁguration 15.5.1 Timing Conﬁguration If BRx[MS] selects the GPCM, the attributes for the memory cycle are taken from ORx. These attributes include the CSNT, ACS[0–1], SCY[0–3], TRLX, EHTR, and SETA ﬁelds.
Page 436: Chip-Select Assertion Timing
• One quarter of a clock cycle later • One half of a clock cycle later Figure 15-16 shows a basic connection between the MPC850 and an external peripheral device. Here, CS (the strobe output for the memory access) is connected directly to CE of the memory device and R/W is connected to the respective R/W in the peripheral device.
Page 437: Chip-Select And Write Enable Deassertion Timing
Figure 15-17. GPCM Peripheral Device Basic Timing (ACS = 1x and TRLX = 0) 15.5.1.2 Chip-Select and Write Enable Deassertion Timing Figure 15-18 shows a basic connection between the MPC850 and a static memory device. Here, CS is connected directly to CE of the memory device. The WE signals are connected to the respective W signal in the memory device where each WE corresponds to a different data byte.
Page 438 Figure 15-19. When ACS ≠ 00 and CSNT = 1, WE and CS are negated one quarter of a clock earlier, as shown in Figure 15-20. Clock Address CSNT = 1 Data Figure 15-19. GPCM Memory Device Basic Timing (ACS = 00, CSNT = 1, TRLX = 0) MPC850 Family User’s Manual...
Page 439: Relaxed Timing
ORx[TRLX] is provided for memory systems that require more relaxed timing between signals. When TRLX = 1 and ACS ≠ 00, an additional cycle between the address and strobes is inserted by the MPC850 memory controller. See Figure 15-21 and Figure 15-22. Clock...
Page 440 (SETA and TRLX = 1), the memory controller does not support external devices that provide TA to complete the transfer with zero wait states. The minimum access duration in this case is 3 clock cycles. MPC850 Family User’s Manual...
Page 441 General-Purpose Chip-Select Machine (GPCM) Clock Address ACS = 10 ACS = 11 Data Figure 15-23. GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 1, TRLX =1) Clock Address Data Figure 15-24. GPCM Relaxed-Timing Write (ACS = 00, SCY = 0, CSNT = 1, TRLX =1) Chapter 15.
Page 442: Output Enable (Oe) Timing
Slow memory devices that take a long time to turn off their data bus drivers on read accesses should set ORx[EHTR]. Any MPC850 access to the external bus following a read access to the slower memory bank is delayed by one clock cycle, unless it is a read access to the same bank.
Page 443 General-Purpose Chip-Select Machine (GPCM) Clock Address Data Hold Time Long hold time allowed Figure 15-26. GPCM Read Followed by Write (EHTR = 1) Clock Address Data Hold Time Long hold time allowed Figure 15-27. GPCM Read Followed by Read from Different Banks (EHTR = 1) Chapter 15.
Page 444: Boot Chip-Select Operation
The CS0 signal is the boot chip-select output and its operation differs from the other external chip-select outputs on system reset. When the MPC850 internal core begins accessing memory at system reset, CS0 is asserted for every address, unless an internal register is accessed.
Page 445: External Asynchronous Master Support
EHTR 15.5.3 External Asynchronous Master Support Figure 15-29 shows the basic interface between an asynchronous external master and the GPCM to allow connection to static RAM. ASYNCHRONOUS EXTERNAL MASTER AS Address Data MPC850 MEMORY Address Address Data Data Figure 15-29. Asynchronous External Master Configuration for GPCM-Handled...
Page 446: Special Case: Bursting With External Transfer Acknowledge:
The GPCM is the subsystem of the memory controller that supports provision of chip-select signals (CSx) for slaves that provide their TA signal external to the MPC850 (ORx[SETA] = 1). However, the GPCM keeps its chip-select asserted only until the ﬁrst TA is sampled.
Page 447: User-Programmable Machines (Upms)
Note also the following: • Address incrementing is not provided in this mode. Addresses driven by the MPC850 remain the same throughout the cycle. • The external slave must provide TA for all beats of the burst. 15.6 User-Programmable Machines (UPMs) The two user-programmable machines (UPMs) are ﬂexible interfaces that connect to a wide...
Page 448: Requests
When an internal master requests a new access to external memory, the address and type of transfer are compared to each valid bank deﬁned in BRx. The value in BRx[MS] selects the UPM to handle the memory access. The user must ensure that the UPM is appropriately initialized before a request. MPC850 Family User’s Manual...
Page 449: Upm Periodic Timer Requests
LAST bit set. 15.6.1.4 Exception Requests When the MPC850 under UPM control initiates an access to a memory device, the external device may assert TEA, SRESET, or HRESET. The UPM provides a mechanism by which memory control signals can meet the timing requirements of the device without losing data.
Page 450: Programming The Upm
Figure 15-34. UPM Clock Scheme One (Division Factor = 1) In Figure 15-35, if SCCR[EBDF] = 01, CLKOUT equals the system clock divided by 2. In this scheme GCLK1_50 does not have a 50% duty cycle. MPC850 Family User’s Manual...
Page 451 The state of the external signals may change (if speciﬁed in the RAM array) at any edge of GCLK1_50 and GCLK2_50, plus a propagation delay, speciﬁed in the MPC850 Hardware Speciﬁcations. Note however that only the CS signal corresponding to the currently accessed bank will be manipulated by the UPM pattern when it runs.
Page 452 CST2 CST3 GPL1 G1T4 G1T3 G1T4 G1T4 G1T3 GPL2 G2T4 G2T3 G2T4 G1T4 G2T3 Clock Phase RAM Word 1 RAM Word 2 Figure 15-37. UPM Signals Timing Example Two (Division Factor = 2, EBDF = 01) MPC850 Family User’s Manual...
Page 453: The Ram Array
User-Programmable Machines (UPMs) 15.6.4 The RAM Array The RAM array for each UPM is 64 locations deep and 32 bits wide, as shown in Figure 15-38. The signals at the bottom of Figure 15-38 are UPM outputs. The selected CS is for the bank that matches the current address.
Page 454 0 Asserted at the rising edge of GCLK2_50. 1 Negated at the rising edge of GCLK2_50 The ﬁnal value of the BS lines depends on the values of BRx[PS], the TSIZ lines, and A[30–31] for the access. See Section 15.6.4.3, “Byte-Select Signals (BSTx).” MPC850 Family User’s Manual...
Page 455 User-Programmable Machines (UPMs) Table 15-14. RAM Word Bit Settings (Continued) Name Description BST3 Byte-select timing 3. Deﬁnes the state of BS during clock phase 4. 0 Asserted at the falling edge of GCLK1_50. 1 Negated at the falling edge of GCLK1_50. The ﬁnal value of the BS lines depends on the values of BRx[PS], the TSIZ lines, and A[30–31] for the access.
Page 456 If the accessed bank has an 8-bit port size, the value is incremented by 1. Note: The value of NA is relevant only when the UPM serves a burst-read or burst-write request. NA is reserved under other patterns. MPC850 Family User’s Manual...
Page 457: Chip-Select Signals (Cstx)
User-Programmable Machines (UPMs) Table 15-14. RAM Word Bit Settings (Continued) Name Description UPM transfer acknowledge. Controls the state of TA sampled by the external bus interface in the current memory cycle. TA is output at the rising edge of GCLK2_50. 0 TA is driven low on the rising edge of GCLK2_50.
Page 458: Byte-Select Signals (Bstx)
Table 15-15. Enabling Byte-Selects Address 32-Bit Port Size 16-Bit Port Size 8-Bit Port Size Transfer TSIZ Size BS0 BS1 BS2 BS3 BS0 BS1 BS2 BS3 BS0 BS1 BS2 BS3 Byte Half-Word Word MPC850 Family User’s Manual...
Page 459: General-Purpose Signals (Gxtx, G0X)
User-Programmable Machines (UPMs) 15.6.4.4 General-Purpose Signals (GxTx, G0x) The general-purpose signals (GPL[1–5]) have two bits in the RAM word that deﬁne the logical value of the signal to be changed at the falling edge of GCLK1_50 or GCLK2_50. GPL0 has two 2-bit ﬁelds that perform this function plus an additional function explained below.
Page 460: Loop Control (Loop)
ﬁeld shown in Table 15-17. The next RAM word for which LOOP = 1 is recognized as a loop end word. When it is reached, the loop counter is decremented by one. MPC850 Family User’s Manual...
Page 461: Exception Pattern Entry (Exen)
Note that this feature of internally multiplexing address signals should only be used in a system where the MPC850 is the only external bus master. If other devices can be bus masters, address multiplexing must be done in external logic. One of the UPM’s output signals can be used to control this external multiplexing logic;...
Page 462 — A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 Address Multiplexing A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 is Enabled — A10 A11 A12 A13 A14 A15 A16 A17 A18 MPC850 Family User’s Manual...
Page 463 User-Programmable Machines (UPMs) Table 15-19 shows how AMx can be deﬁned to interface with a range of DRAM modules. Table 15-19. AMA/AMB Definition for DRAM Interface DRAM Address Pin Number Data Bus MPC850 Address Memory Size Width Pin Connection Column...
Page 464 8 Mbyte A20–A31 16 Mbyte A19–A31 32 Mbyte A18–A31 64 Mbyte A17–A31 16 Mbyte A20–A31 32 Mbyte A19–A31 64 Mbyte A18–A31 128 Mbyte A17–A31 256 Mbyte A16–A31 64 Mbyte A19–A31 128 Mbyte A18–A31 256 Mbyte A17–A31 MPC850 Family User’s Manual...
Page 465 User-Programmable Machines (UPMs) Table 15-19. AMA/AMB Definition for DRAM Interface (Continued) DRAM Address Pin Number Data Bus MPC850 Address Memory Size Width Pin Connection Column 16 bits 128 Kbyte A23–A30 256 Kbyte A22–A30 512 Kbyte A21–A30 1 Mbyte A20–A30 2 Mbyte A19–A30...
Page 466: Transfer Acknowledge And Data Sample Control (Uta, Dlt3)
GCLK2_50 instead of the rising edge, which is normal. This feature lets the user speed up the memory interface by latching data 1/2 clock early, which can be useful during burst reads. This feature should be used only in systems without external synchronous bus devices. MPC850 Family User’s Manual...
Page 467: Disable Timer Mechanism (Todt)
User-Programmable Machines (UPMs) • If G4T4/DLT3 functions as G4T4, data is latched on the rising edge of the external bus clock, as is normal in MPC850 bus operation. Figure 15-44 shows data sampling that is controlled by the UPM. Latch...
Page 468: External Asynchronous Masters
UTA = 0 in the same RAM word in which WAEN = 1. If this is done, TA can be used to signal that AS should deassert (similar to DTACK in the 68000 bus). MPC850 Family User’s Manual...
Page 469: Handling Devices With Slow Or Variable Access Times
Handling Devices with Slow or Variable Access Times The wait state is exited when AS is negated, at which point all external signals controlled by the UPM are driven high asynchronously from the AS deassertion. External signals are driven in this state until the LAST bit is set in a RAM word. The TODT bit is relevant only in words read by the UPM after AS is negated.
Page 470: Hierarchical Bus Interface Example
MPC850 memory controller to access a slave. • Asynchronous bus masters use an address strobe signal (AS) that handshakes with the MPC850 memory controller to access a slave device or bypass the memory controller to perform the slave access. 15.8.1 Synchronous External Masters Synchronous masters initiate a transfer by asserting TS.
Page 471: Asynchronous External Masters
AS. If AEME = 0, the memory controller is bypassed and the external asynchronous master must provide control signals to the slave. In this mode, the MPC850’s AS signal cannot be used as an input. See Figure 15-48. 15.8.3 Special Case: Address Type Signals for External Masters The AT signals are not sampled on the external bus for external master accesses.
Page 472: Handshake Mechanism For Asynchronous External Masters
Section 15.6.4.11, “The Wait Mechanism (WAEN).” 15.8.4.3 Special Signal for External Address Multiplexer Control If external masters exist in the system with the MPC850, address multiplexing (for DRAM for example) must be implemented in external logic. To control this external multiplexer, special features have been added to GPL5.
Page 473 External Master Support CLKOUT A[6–27] A[28–31] BURST TSIZ Data Address Memory Match and Device Compare Access Figure 15-47. Synchronous External Master Access Chapter 15. Memory Controller...
Page 474: External Masters And The Upm
Figure 15-49 shows a synchronous interconnection in which an external master and the MPC850 can share access to a DRAM bank. Notice that CS1, UPMA, and GPL_A5 were chosen to help control DRAM bank accesses. To perform burst accesses initiated by the external master or MPC850 using this conﬁguration, A[28–30] connects to the multiplexer...
Page 475 External Master Support DRAM BS[0–3] Bank GPL_A5 Multiplexer A[6–31] D[0–31] BURST External MPC850 Master TSIZ[0–1] Figure 15-49. Synchronous External Master Interconnect Example Chapter 15. Memory Controller...
Page 476 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RBS+1 RBS+2 RBS+3 RBS+4 RBS+5 RBS+6 RBS+7 RBS+8 Figure 15-50. Synchronous External Master: Burst Read Access to Page Mode DRAM MPC850 Family User’s Manual...
Page 477 Figure 15-51 shows an asynchronous interconnection in which an external master and the MPC850 can share access to a DRAM bank. Notice that CS1, UPMA, and GPL_A5 were chosen to control DRAM bank accesses. Figure 15-52 shows the timing behavior of GPL_A5 and other control signals when an external master to a DRAM bank initiates a single-beat read.
Page 478 – Bit 23 loop Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RSS+1 WAIT WAIT RSS+2 Figure 15-52. Asynchronous External Master Timing Example MPC850 Family User’s Manual...
Page 479: Memory System Interface Examples
Figure 15-53. Page-Mode DRAM Interface Connection Follow these steps to conﬁgure a system for page mode DRAM: 1. Determine the system architecture, which includes the MPC850 and the memory system as shown in the example in Figure 15-53. 2. Use the blank work sheet in Figure 15-70 to draw the timing diagrams for all the memory cycles.
Page 480 Selects two disable timer clock cycles GPLA4DIS Disables the UPWAITA signal RLFA 0011 Selects three loop iterations for read WLFA 0011 Selects three loop iterations for write Selects column address on ﬁrst cycle Supports burst accesses MPC850 Family User’s Manual...
Page 481 Memory System Interface Examples CLKOUT/GCLK2_50 GCLK1_50 A[6–31] Column D[0–31] CS1 (RAS) BS_A[0–3] (CAS[0–3]) cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6 bst3 Bit 7 g0l0 Bit 8 g0l1 Bit 9 g0h0...
Page 482 Bit 23 loop Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 WSS WSS+1 WSS+2 Figure 15-55. Single-Beat Write Access to Page Mode DRAM MPC850 Family User’s Manual...
Page 483 Memory System Interface Examples CLKOUT/GCLK2_50 GCLK1_50 A[6–31] Column 1 Column 2 Column 3 Column 4 D[0–31] CS1 (RAS) BS_A[0–3] (CAS[0–3]) cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6 bst3 Bit 7 g0l0...
Page 484 Bit 23 loop Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RBS+1 RBS+2 RBS+3 RBS+4 Figure 15-57. Burst Read Access to Page-Mode DRAM (LOOP) MPC850 Family User’s Manual...
Page 485 Memory System Interface Examples CLKOUT/GCLK2_50 GCLK1_50 A[6–31] Column 1 Column 2 Column 3 Column 4 D[0–31] CS1 (RAS) BS_A[0–3] (CAS[0–3]) cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6 bst3 Bit 7 g0l0...
Page 486 Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 WBS WBS+1 WBS+2 WBS+3 WBS+4 Figure 15-59. Burst Write Access to Page-Mode DRAM (LOOP) MPC850 Family User’s Manual...
Page 487 Memory System Interface Examples CLKOUT/GCLK2_50 GCLK1_50 CS1 (RAS) BS_A[0–3] (CAS[0–3]) cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6 bst3 Bit 7 g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10 g0h1...
Page 488 Cycles can be reduced by using faster DRAM or a slower system clock that meets the DRAM access time. For a 16-bit port size memory, the reduction is from 17 to 10 cycles and when an 8-bit port size memory is connected, the reduction is from 33 to 18 cycles. MPC850 Family User’s Manual...
Page 489 Memory System Interface Examples CLKOUT/GCLK2_50 GCLK1_50 A[6–31] Col 1 Col 2 Col 3 Col 4 D[0–31] CS1 (RAS) BS_A[0–3] (CAS[0–3]) cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6 bst3 Bit 7 g0l0...
Page 490: Page Mode Extended Data-Out Interface Example
GPL_B1 is connected to the memory device OE pins. The refresh rate calculation is based on a 25-MHz baud rate generator clock and the DRAM that requires a 512-cycle refresh every 8 ms. This system has no external masters, and thus the MPC850 is conﬁgured to perform address multiplexing internally. MPC850 BS_B[0–3]...
Page 491 Memory System Interface Examples 4. Deﬁne the UPMB (or UPMA) parameters that control the memory system in the following sequence. For additional details, see Table 15-20. — Program the RAM array using MCR and MDR. The RAM word must be written into the MDR before a command is issued to the MCR.
Page 492 – Bit 23 loop Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RSS+1 RSS+2 RSS+3 RSS+4 Figure 15-64. EDO DRAM Single-Beat Read Access MPC850 Family User’s Manual...
Page 493 Memory System Interface Examples CLKOUT/GCLK2_50 GCLK1_50 A[6–31] Column D[0–31] CS2 (RAS) BS_B[0–3] (CAS[0–3]) GPL_B1 (OE) cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6 bst3 Bit 7 g0l0 Bit 8 g0l1 Bit 9...
Page 494 Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 RBS+1 RBS+2 RBS+3 RBS+4 RBS+5 RBS+6 RBS+7 RBS+8 RBS+9 RBS+10 Figure 15-66. EDO DRAM Burst Read Access MPC850 Family User’s Manual...
Page 495 Memory System Interface Examples CLKOUT/GCLK2_50 GCLK1_50 A[6–31] Column 1 Column 2 Column 3 Column 4 D[0–31] CS2 (RAS) BS_B[0–3] (CAS[0–3]) GPL_B1 (OE) cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6 bst3...
Page 496 Bit 23 loop Bit 24 exen Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 PTS+1 PTS+2 PTS+3 PTS+4 Figure 15-68. EDO DRAM Refresh Cycle (CAS before RAS) MPC850 Family User’s Manual...
Page 497 Memory System Interface Examples CLKOUT/GCLK2_50 GCLK1_50 CS2 (RAS) BS_B[0–3] (CAS[0–3]) GPL_B1 (OE) cst4 Bit 0 cst1 Bit 1 cst2 Bit 2 cst3 Bit 3 bst4 Bit 4 bst1 Bit 5 bst2 Bit 6 bst3 Bit 7 g0l0 Bit 8 g0l1 Bit 9 g0h0 Bit 10...
Page 498 Bit 25 amx0 Bit 26 amx1 Bit 27 Bit 28 Bit 29 todt Bit 30 last Bit 31 xxS+1 xxS+2 xxS+3 xxS+4 xxS+5 xxS+6 xxS+7 xxS+8 xxS+9 xxS+10 Figure 15-70. Blank Work Sheet for a UPM MPC850 Family User’s Manual...
Page 499 Chapter 16 PCMCIA Interface The PCMCIA host adapter module provides all control logic for a PCMCIA socket interface, and requires only additional external analog power switching logic and buffering. Additional external buffers allow the PCMCIA host adapter module to support up to two PCMCIA sockets.
Page 500 POE_B A[6–31] Address_B[0–25] REG_B V CC _B Transparent ALE_B Latch with OE WAIT_B, IOIS16_B RDY/BSY_B, BVD1_B, BVD2_B Chip V DD CD1_B, CD2_B, VS1_B, VS2_B Transparent SPKROUT Latch for voltage conversion Figure 16-1. System with PCMCIA Socket MPC850 Family User’s Manual...
Page 501: Pcmcia Cycle Control Signals
Extend bus cycle. Input. Asserted by the PC card to delay completion of the pending memory or I/O cycle. RD/WR External transceiver direction. Output. Asserted during MPC850 read cycles and negated during write cycles. Used in the PCMCIA interface to control the direction of the data bus transceivers.
Page 502: Pcmcia Input Port Signals
8 bits wide, IOIS16_B is ignored. 16.2.2 PCMCIA Input Port Signals The following signals are used by a PCMCIA slot to indicate card status. The MPC850 provides synchronization, transition detection, optional interrupt generation, and the means for the software to read the signal state.
Page 503: Pcmcia Output Port Signals (Op[0–4])
A PCMCIA slot can use the signals in Table 16-3 to control the RESET input and output enable of the buffers to the card. The MPC850 gives software a way to control the output signal state. This function is not necessarily speciﬁc to the PCMCIA interface; a system can use these signals as a general-purpose output port.
Page 504: Memory-Only Cards
(PER) to generate a PCMCIA interface interrupt. The interrupt level is user programmable and the PCMCIA interface can generate an additional interrupt for RDY/IRQ that can trigger on level (low or high) or edge (fall or rise) of the input signal. MPC850 Family User’s Manual...
Page 505: Power Control
PGCRB[CBRESET] and PGCRB[CBOE], respectively. 16.3.6 DMA The MPC850 DMA module with the CPM microcode provides two independent DMA (IDMA) channels. See Section 19.3, “IDMA Emulation.” The PCMCIA module can be programmed to generate control for an I/O device implemented as a PCMCIA card to respond to DMA transfer.
Page 506: Programming Model
(IMMR & 0xFFFF0000) + 0x0F0 24 25 26 27 28 29 30 31 Field CBVS1 CBVS2 CBWP CBCD2 CBCD1 CBBVD2 CBBVD1 CBRDY — Reset Undeﬁned Addr (IMMR & 0xFFFF0000) + 0x0F2 Figure 16-3. PCMCIA Interface Input Pins Register (PIPR) MPC850 Family User’s Manual...
Page 507: Pcmcia Interface Status Changed Register (Pscr)
Programming Model Table 16-8 describes PIPR ﬁelds. Table 16-8. PIPR Field Descriptions Bits Name Description 0–15 — Reserved, should be cleared. CBVS1 Voltage sense 1 for card B CBVS2 Voltage sense 2 for card B CBWP Write protect for card B CBCD2 Card detect 2 for card B CBCD1...
Page 508: Pcmcia Interface Enable Register (Per)
Table 16-10 describes PER ﬁelds. Table 16-10. PER Field Descriptions Bits Name Description 0–15 — Reserved, should be 0. CB_EVS1 Enable for voltage sense 1 for card B changed. Setting this bit enables the interrupt on any signal change. MPC850 Family User’s Manual...
Page 509: Pcmcia Interface General Control Register B (Pgcrb)
Programming Model Table 16-10. PER Field Descriptions (Continued) Bits Name Description CB_EVS2 Enable for voltage sense 2 for card B changed. Setting this bit enables the interrupt on any signal change. CB_EWP Enable for write protect for card B changed. Setting this bit enables the interrupt on any signal change.
Page 510: Pcmcia Base Registers 0–7 (Pbr0–Pbr7)
PBA is used in conjunction with POR[BSIZE]. 16.4.6 PCMCIA Option Register 0–7 (POR0–POR7) The POR, shown in Figure 16-8, as the manipulation of timing, provides the address mask for the bank size, and deﬁnes the region, slot, write protection, and validation. MPC850 Family User’s Manual...
Page 511 Programming Model Field BSIZE — PSHT Reset Undeﬁned Addr (IMMR & 0xFFFF0000) + 0x084 (POR0); 0x08C (POR1); 0x094 (POR2); 0x09C (POR3); 0x0A4 (POR4); 0x0AC (POR5); 0x0B4 (POR6); 0x0BC (POR7) Field PSST PSLOT Reset Undeﬁned Addr (IMMR & 0xFFFF0000) + 0x086 (POR0); 0x08E (POR1); 0x096 (POR2); 0x09E (POR3); 0x0A6 (POR4); 0x0AE (POR5);...
Page 512 PCMCIA interface. This helps meet address/setup time requirements for slow memories and peripherals. 0000 Reserved 0001 Address to strobe assertion 1 clock cycle 0010 Address to strobe assertion 2 clock cycles 1111 Address to strobe assertion 15 clock cycles MPC850 Family User’s Manual...
Page 513 Programming Model Table 16-13. POR Field Descriptions (Continued) Bits Name Description 20–24 PCMCIA strobe length. Determines the number of cycles the strobe is asserted during a PCMCIA access for this window and, thus, it is the main parameter for determining cycle length. The cycle may be lengthened by asserting WAIT.
Page 514: Pcmcia Controller Timing Examples
PCMCIA Controller Timing Examples 16.5 PCMCIA Controller Timing Examples CLKOUT A[6–31] RD/WR BURST CE1/CE2 PCOE WAIT Data PSST PSHT Figure 16-9. PCMCIA Single-Beat Read Cycle PRS = 0 PSST = 1 PSL = 3 PSHT = 1 MPC850 Family User’s Manual...
Page 515 PCMCIA Controller Timing Examples CLKOUT A[6–31] RD/WR BURST CE1/CE2 PCOE WAIT Data PSST PSHT Figure 16-10. PCMCIA Single-Beat Read Cycle PRS = 0 PSST = 2 PSL = 4 PSHT = 1 Chapter 16. PCMCIA Interface...
Page 516 PCMCIA Controller Timing Examples CLKOUT A[6–31] RD/WR BURST CE1/CE2 PCOE WAIT Data PSHT PSST Figure 16-11. PCMCIA Single-Beat Read Cycle PRS = 0 PSST = 1 PSL = 3 PSHT = 0 MPC850 Family User’s Manual...
Page 517 PCMCIA Controller Timing Examples CLKOUT A[6–31] RD/WR BURST CE1/CE2 PCWE WAIT Data PSST PSHT Figure 16-12. PCMCIA Single-Beat Write Cycle PRS = 2 PSST = 1 PSL = 3 PSHT = 1 Chapter 16. PCMCIA Interface...
Page 518 PCMCIA Controller Timing Examples CLKOUT A[6–31] RD/WR BURST CE1/CE2 IOWR WAIT Data IO16 PSST PSHT Figure 16-13. PCMCIA Single-Beat Write Cycle PRS = 3 PSST = 1 PSL = 4 PSHT = 3 MPC850 Family User’s Manual...
Page 519 PCMCIA Controller Timing Examples CLKOUT A[6–31] RD/WR BURST CE1/CE2 IOWR WAIT Data PSHT PSST Wait Delay Figure 16-14. PCMCIA Single-Beat Write with Wait PRS = 3 PSST = 1 PSL = 3 PSHT = 0 Chapter 16. PCMCIA Interface...
Page 520 PCMCIA Controller Timing Examples CLKOUT A[6–31] RD/WR BURST CE1/CE2 IORD WAIT Data PSST Wait Delay PSHT Figure 16-15. PCMCIA Single-Beat Read with Wait PRS = 3 PSST = 1 PSL = 3 PSHT =1 MPC850 Family User’s Manual...
Page 521 PCMCIA Controller Timing Examples CLKOUT A[6–31] RD/WR BURST IOWR Data IO16 PSHT PSST Figure 16-16. PCMCIA I/O Read PPS = 1 PRS = 3 PSST = 1 PSL = 2 PSHT = 0 Chapter 16. PCMCIA Interface...
Page 522 PCMCIA Controller Timing Examples CLKOUT A[6–31] RD/WR BURST IOWR Data IO16 PSHT PSHT PSST PSST Figure 16-17. PCMCIA I/O Read PPS = 1 PRS = 3 PSST = 1 PSL = 2 PSHT = 0 MPC850 Family User’s Manual...
Page 523 PCMCIA Controller Timing Examples CLKOUT A[6–31] AT = 0xF AT = 0xF RD/WR BURST CE1/CE2 IORD PCOE SIZE SIZE = Word SIZE = Half Data PSHT PSHT PSST PSST Figure 16-18. PCMCIA DMA Read Cycle PRS = 4 PSST = 1 PSL = 3 PSHT = 0 Chapter 16.
Page 524 PCMCIA Controller Timing Examples MPC850 Family User’s Manual...
Page 525: Communications Processor Module
Intended Audience Part V is intended for system designers who need to implement various communications protocols on the MPC850. It assumes a basic understanding of the PowerPC exception model, the MPC850 interrupt structure, as well as a working knowledge of the communications protocols to be used.
Page 526: Scc Ethernet Mode
• Chapter 32, “Universal Serial Bus Controller,” describes the MPC850 implementation of the universal serial bus, an industry-standard extension to the PC architecture that supports data exchange between the MPC850 and a PC host and a wide range of simultaneously accessible peripherals.
Page 527 This section lists additional reading that provides background for the information in this manual as well as general information about the PowerPC architecture. MPC8xx Documentation Supporting documentation for the MPC850 can be accessed through the world-wide web at http://www.motorola.com/SPS/RISC/netcomm. This documentation includes technical speciﬁcations, reference materials, and detailed applications notes.
Page 528 (such as SDR1 and DSISR) are historical, and the words for which an acronym stands may not be intuitively obvious. Table vi. Acronyms and Abbreviated Terms Term Meaning Arithmetic logic unit Asynchronous transfer mode Buffer descriptor MPC850 Family User’s Manual...
Page 529 Table vi. Acronyms and Abbreviated Terms (Continued) Term Meaning BIST Built-in self test CEPT Conference des administrations Europeanes des Postes et Telecommunications (European Conference of Postal and Telecommunications Administrations). Condition/indication channel used in the GCI protocol Communications processor Communications processor module Direct memory access DPLL Digital phase-locked loop...
Page 530 Systems network architecture Serial peripheral interface SRAM Static random access memory Time-division multiplexed Terminal endpoint of an ISDN connection Translation lookaside buffer Time-slot assigner Transmit UART Universal asynchronous receiver/transmitter User-programmable machine USART Universal synchronous/asynchronous receiver/transmitter Universal serial bus MPC850 Family User’s Manual...
Page 531: Features
• By supporting multibuffer memory data structures that are convenient for software handling. The MPC850 CPM is similar to the one in the MPC860 and both are derived from the CPM in the MC68360 QUICC; see the MC68360 Quad Integrated Communications Controller (QUICC) User’s Manual.
Page 532: Risc Timer Tables
The following lists the CPM’s main features: • Communications processor (CP) — Dual-port RAM — Internal ROM — DMA control for all communications channels — Two independent DMA channels for memory-to-memory transfers or interfacing external peripherals — RISC timer tables MPC850 Family User’s Manual...
Page 533 • Four general-purpose 16-bit timers or two 32-bit timers • CPM interrupt controller (CPIC) • General-purpose I/O ports Figure 17-2 shows a possible MPC850 conﬁguration for a multiprotocol application that supports various communications links and protocols. Chapter 17. Communications Processor Module and CPM Timer...
Page 534: Cpm General-Purpose Timers
• Timer counter (TCN) • Timer reference register (TRR) • Timer event register (TER) • Timer global conﬁguration register (TGCR). NOTE: Mask revision F98S contains only two timers, Timer1 and Timer2, and two baud rate generators, BRG1 and BRG2. MPC850 Family User’s Manual...
Page 535: Features
CPM General-Purpose Timers Figure 17-3 is a block diagram of the CPM timers. General System Clock TGCR Global Configuration Register TGATE1 TER1 Timer Event Register Clock Generator TIN1 Mode Register TMR1 Prescaler Mode Bits TIN2 TIN3 Divider Clock TIN4 TCN1 Timer Counter (TCN) Capture Detection...
Page 536: Cpm Timer Operation
TINx is sensed by the corresponding input capture edge detector. The type of transition triggering the capture is selected by TMRx[CE]. When a capture or reference event occurs, the corresponding TERx event bit is set and a maskable interrupt request is issued to the CPIC. MPC850 Family User’s Manual...
Page 537: Timer Gating (Timers 1 And 2 Only)
CPM General-Purpose Timers 17.2.2.4 Timer Gating (Timers 1 and 2 only) Timers 1 and 2 can be gated or restarted by an external gate signal—TGATE1. Normal gate mode enables the count on a falling edge of TGATE1 and disables the count on the rising edge of TGATE1.
Page 538: Timer 1 And Spkrout
1, 5, 9, 13 0 The corresponding timer ignores the FRZ state. 1 Stops the corresponding timer if the MPC850 enters FRZ state. FRZ state is entered in debug mode as deﬁned in Chapter 44, “System Development and Debugging.” STPx Stop timer x.
Page 539: Timer Mode Registers (Tmr1–Tmr4)
CPM General-Purpose Timers Table 17-1. TGCR Field Descriptions (Continued) Bits Name Description CAS2 Cascade timers. 0 Normal operation. 1 Timers 1 and 2 are cascaded to form a 32-bit timer. Gate mode for TGATE1. Valid only if TMR1[GE] or TMR2[GE] is set. 0 Restart gate mode.
Page 540: Timer Reference Registers (Trr1–Trr4)
Each timer capture register (TCR1–TCR4), shown in Figure 17-8, is used to latch the value of the counter according to TMRx[CE]. Field Latched counter value Reset Addr 0x998 (TCR1), 0x99A (TCR2), 0x9A8 (TCR3), 0x9AA (TCR4) Figure 17-8. Timer Capture Registers (TCR1–TCR4) MPC850 Family User’s Manual...
Page 541: Timer Counter Registers (Tcn1–Tcn4)
CPM General-Purpose Timers 17.2.4.3 Timer Counter Registers (TCN1–TCN4) Each timer counter register (TCN1–TCN4), shown in Figure 17-9, is an up-counter. A read cycle to TCN1–TCN4 yields the current value of the timer, but does not affect the counting operation. A write cycle to TCN1–TCN4 sets the register to the written value, thus causing its corresponding prescaler, TMRx[PS], to be reset.
Page 542: Timer Initialization Examples
6. Write TER2 = 0xFFFF to clear TER2 of any previous events. 7. Set CIMR = 0x0004_0000 to enable timer 2 interrupts in the CPIC and initialize the CICR. 8. Set TGCR = 0x0091 to enable timers 1 and 2 to begin counting in cascaded mode. MPC850 Family User’s Manual...
Page 543: Features
Chapter 18 Communications Processor Transacting with the communications peripherals on a separate bus from the PowerPC core, the CPM’s 32-bit communications processor (CP) handles the low-level communications tasks, freeing the core for higher-level tasks. The CP implements the chosen protocols using the serial controllers and parallel interface port and manages the data transfer through the serial DMA (SDMA) channels between the I/O channels and memory.
Page 544: Communicating With The Core
FIFOs. The SCC2 receive and transmit FIFOs are 32 bytes each; the USB and SCC3 FIFOs are 16 bytes each. The serial management controllers (SMCs), serial peripheral interface (SPI), and I C are all double-buffered, creating effective FIFO sizes of two characters. MPC850 Family User’s Manual...
Page 545: Cp Microcode Revision Number
CP Microcode Revision Number Table 18-1 shows the order in which the CP handles requests from peripherals from highest to lowest priority. Table 18-1. Peripheral Prioritization Priority Request Reset in the CPCR or SRESET SDMA bus error Commands issued to the CPCR IDMA emulation: DREQ0 (default—option 1) IDMA emulation: DREQ1 (default—option 1) USB Rx...
Page 546: Cp Register Set And Cp Commands
= (TIMEP + 1) × 1,024 system clocks. Thus, a value of 0 stored in this ﬁeld creates a timer tick every 1 × (1,024) = 1,024 system clocks; a value of 63 causes a tick every 64 × (1,024) = 65,536 system clocks. MPC850 Family User’s Manual...
Page 547: Risc Microcode Development Support Control Register (Rmds)
CP Register Set and CP Commands Table 18-3. RCCR Field Descriptions (Continued) Bits Name Description DR1M IDMA request 1 mode. Controls the IDMA request 1 (DREQ1) sensitivity mode. See Section 19.3.7, “IDMA Interface Signals—DREQ and SDACK.” 0 DREQ1 is edge-sensitive. 1 DREQ1 is level-sensitive.
Page 548: Cp Command Register (Cpcr)
CPM and RISC timer table. RST does not, however, affect the serial interface or parallel I/O registers. 0 No reset issued. 1 Reset issued. 1–3 — Reserved. Should be cleared. 4–7 OPCODE Operation code for the core-issued CP commands. See Table 18-7. MPC850 Family User’s Manual...
Page 549: Cp Commands
CP Register Set and CP Commands Table 18-5. CPCR Field Descriptions (Continued) Bits Name Description 8–11 CH_NUM Channel number. Deﬁnes the speciﬁc sub-block on which the command is to operate. Some sub-blocks share channel number encodings if their commands are mutually exclusive. 0000 USB 0001 I C/IDMA1...
Page 550 Sets a hash table bit for the Ethernet logical group address recognition function. SET GROUP ADDRESS GCI receiver sends an abort request. GCI ABORT REQUEST Performs the GCI timeout function. GCI TIMEOUT Used in BISYNC mode to reset the block check sequence calculation. RESET BCS MPC850 Family User’s Manual...
Page 551: Cp Command Examples
Dual-Port RAM Table 18-7. CP Commands (Continued) Command Description USB command code. The speciﬁc USB commands are described in Section 32.9, “USB CP USB COMMAND Commands.” Undeﬁned. Reserved for use by Motorola-supplied RAM microcode packages. 18.5.4.1 CP Command Examples To completely reset the CPM, write 0x8001 to the CPCR. After two clocks, the CPCR should return a 0x0000 value.
Page 552 The controller and sub-block parameters of the parameter RAM and the optional microcode packages in system RAM use ﬁxed addresses. The buffer descriptors, buffers, and scratch pad area, however, can be located in any unused dual-port RAM area. See Figure 18-6. MPC850 Family User’s Manual...
Page 553: System Ram And Microcode Packages
Dual-Port RAM 0 Kbyte IMMR + 0x2000 ERAM = 11 ERAM = 10 ERAM = 01 BD/Data/Microcode IMMR + 0x2200 BD/Data/Microcode 1 Kbyte IMMR + 0x2400 BD/Data/Microcode 2 Kbyte IMMR + 0x2800 BD/Data 3 Kbyte IMMR + 0x2E00 ERAM = 11 BD/Data/Microcode ERAM = 01, 10 IMMR + 0x2F00...
Page 554: The Buffer Descriptor (Bd)
Page Offset from DPRAM_base Controller/Peripheral 0x3C00 0x1C00—0x1C7F 0x1C80—0x1CAF 0x1CB0—0x1CBF Miscellaneous 0x1CC0—0x1CFF IDMA1 0x3D00 0x1D00—0x1D7F SCC2 0x1D80—0x1DAF 0x1DB0—0x1DBF RISC timer table 0x1DC0—0x1DFF IDMA2 0x3E00 0x1E00—0x1E7F SCC3 0x1E80—0x1EBF SMC1 0x1EC0—0x1EFF Reserved 0x3F00 0x1F00—0x1F7F Reserved 0x1F80—0x1FBF SMC2 0x1FC0—0x1FFF Reserved MPC850 Family User’s Manual...
Page 555: The Risc Timer Table
The RISC Timer Table The SPI and I C parameter RAM areas can be relocated to other 32-byte aligned parameter areas in dual-port RAM by programming their 16-bit base offsets, shown in Table 18-10. Table 18-10. I C and SPI Parameter RAM Relocation Offset from DPRAM_base Size Controller/Peripheral...
Page 556: Risc Timer Table Scan Algorithm
Timer Table Base Pointer DPRAM_BASE + 0x1DB0 TM_BASE RISC Timer Table Parameter RAM Figure 18-7. RISC Timer Table RAM Usage The RISC timer table parameter RAM holds the general timer parameters. Table 18-11 shows its memory map. MPC850 Family User’s Manual...
Page 557: Risc Timer Command Register (Tm_Cmd)
The RISC Timer Table Table 18-11. RISC Timer Table Parameter RAM Memory Map Offset Name Width Description TM_BASE Hword RISC timer table base address. The actual timers are a small block of memory in the 0x00 dual-port RAM. TM_BASE is the offset from the beginning of the dual-port RAM where that block of memory resides.
Page 558: Risc Timer Table Entries
Section 35.5.3, “CPM Interrupt Mask Register,” acts as a global RISC timer interrupt mask. Clearing CIMR[RTT] masks all RISC timer interrupts, regardless of RTMR. 18.7.5 PWM Mode Designated pairs of timers can be used to generate PWM waveforms through port B. A maximum of eight channels are supported. MPC850 Family User’s Manual...
Page 559: Risc Timer Initialization
The RISC Timer Table The ﬁrst timer (even numbered) determines the duty cycle of the waveform: • Program TM_CMD[Timer Period] to be the high period of the waveform. • Set TM_CMD[V, PWM]. The second timer (odd numbered) determines the overall period: •...
Page 560: Risc Timer Interrupt Handling
The RISC timers can be used to track CP loading. The following sequence is a method for using the 16 RISC timers to determine if the CP ever exceeds the 96% utilization level during a scan tick interval. Removing the timers adds a 4% margin to the CP’s utilization MPC850 Family User’s Manual...
Page 561 The RISC Timer Table level, but an aggressive user can use this technique to push the CP performance to its limit. Incorporate the following steps to the standard initialization sequence: 1. Program RCCR[TIMEP] to 0b001111 for a table scan tick of 16 × (1,024) = 16,384. 2.
Page 562 The RISC Timer Table MPC850 Family User’s Manual...
Page 563: Sdma Channels
Chapter 19 SDMA Channels and IDMA Emulation The CPM controls two physical serial DMA (SDMA) channels on the MPC850. Using the two physical channels, the CP implements 20 virtual SDMA channels, each dedicated to a serial controller transmitter or receiver—eight for the USB, four for the full-duplex SCCs, and the remaining eight for the SPI, I C, and the two SMCs.
Page 564: Sdma Transfers
An external request loses ties to an internal request or DRAM refresh request with the same arbitration ID. For example, if SIUMCR[EARP] is 4, the external master has priority over the I-cache but not over the D-cache. MPC850 Family User’s Manual...
Page 565: Sdma Registers
SDMA Registers Once an SDMA channel obtains the external system bus, it remains master for the whole transaction—a byte, half-word, word or burst transfer—before relinquishing the bus. This feature, in combination with the zero-clock arbitration overhead provided by the U-bus, increases bus efﬁciency and lowers latency.
Page 566: Sdma Configuration Register (Sdcr)
SDMA controller recognizes a bus error, it sets the corresponding event bit in the SDSR. SDSR bits are cleared by writing ones; writing zeros has no effect. Figure 19-4 shows the register format. Field SBER — Reset 0000_0000 Addr IMMR + 0x908 Figure 19-4. SDMA Status Register (SDSR) MPC850 Family User’s Manual...
Page 567: Sdma Mask Register (Sdmr)
IDMA Emulation Table 19-3 describes the SDSR bit settings. Table 19-3. SDSR Field Descriptions Bits Name Description SBER SDMA channel bus error. Indicates an error caused the SDMA channel to terminate during a read or write cycle. The SDMA bus error address can be retrieved from the SDMA address register (SDAR). 1–7 —...
Page 568: Idma Features
• Optimized, low-overhead single-buffer mode for peripheral-to-memory transfers on IDMA1 • The MPC850’s chip-select and wait-state generation logic can be used with IDMA. 19.3.2 IDMA Parameter RAM Both IDMA channels have a dedicated portion of dual-port RAM for channel parameters.
Page 569: Idma Registers
IDMA Emulation Table 19-4. IDMA Parameter RAM Memory Map (Continued) 0x0C IBPTR Hword Current IDMA BD pointer. If the IDMA channel is idle, IBPTR points to the next valid BD in the table. After a reset, or when the end (wrap bit) of the BD table is reached, the CP wraps IBPTR back to IBASE.
Page 570: Idma Status Registers (Idsr1 And Idsr2)
Figure 19-6. IDMA Status Registers (IDSR1/IDSR2) Table 19-6 describes the IDSR ﬁelds. Table 19-6. IDSR1/IDSR2 Field Descriptions Bits Name Description 0–4 — Reserved Auxiliary done. Set after processing a BD that has its I bit (interrupt) set. MPC850 Family User’s Manual...
Page 571: Idma Mask Registers (Idmr1 And Idmr2)
IDMA Emulation Table 19-6. IDSR1/IDSR2 Field Descriptions (Continued) Bits Name Description DONE Buffer chain done. Indicates IDMA transfer termination. Set after servicing a BD that has its L bit (last) set, regardless of the I bit setting. Out of buffers. Indicates that the IDMA channel has no valid BDs left in the BD table. 19.3.3.3 IDMA Mask Registers (IDMR1 and IDMR2) The read/write IDMA mask registers (IDMR1 and IDMR2) have the same format as IDSR, shown in Figure 19-6.
Page 572 0 Not the last descriptor in the BD table. 1 Last descriptor in the BD table. After this descriptor has been processed, the CP wraps the current BD pointer (IBPTR) back to the top of the BD table (IBASE). MPC850 Family User’s Manual...
Page 573: Function Code Registers—Sfcr And Dfcr
IDMA Emulation Table 19-7. IDMA BD Status and Control Bits (Continued) Bits Name Description Interrupt. Enable the maskable auxiliary-done (AD) interrupt. 0 IDSR[AD] is not ﬂagged after this BD is processed. 1 IDSR[AD] is ﬂagged after this BD is processed. Last.
Page 574: Auto-Buffering And Buffer-Chaining
See Section , “The PowerPC core can issue commands to control communications via the CP command register (CPCR), shown in Figure 18-4. The CP commands handle special cases, such as initializing or stopping a channel, and are protocol-dependent.,” for the mechanics of issuing CP commands. MPC850 Family User’s Manual...
Page 575: Idma Channel Operation
(DREQ) and SDMA acknowledge (SDACK). DREQ0 and SDACK1 are dedicated to IDMA1, while DREQ1 and SDACK2 are for IDMA2. DREQ and SDACK are the handshake signals between the MPC850 and an external peripheral requesting service. A peripheral requests IDMA service directly to the CPM by asserting DREQ.
Page 576: Idma Requests For Memory/Memory Transfers
DMA transfers are performed, the peripheral must negate DREQ while the IDMA is acknowledging the last data move, that is, while SDACK is asserted. DREQ is sampled on the same rising edge on which TA is sampled to terminate the current cycle. MPC850 Family User’s Manual...
Page 577: Edge-Sensitive Requests
IDMA Emulation 19.3.7.2.2 Edge-Sensitive Requests Clearing RCCR[DRnM] makes the corresponding IDMA channel edge-sensitive to requests. The edge sensitivity is further qualiﬁed to detect either any edge or falling edges only as programmed in PCINT[EDM15] and PCINT[EDM14] for DREQ0 and DREQ1, respectively;...
Page 578: Single-Address (Single-Cycle) Transfer (Fly-By)
See Section 19.3.7, “IDMA Interface Signals—DREQ and SDACK,” for more on IDMA handshake signals. CLKOUT Address SETUP HOLD Data SDACK DELAY PHOLD Figure 19-10. SDACK Timing Diagram: Single-Address Peripheral Write, Externally-Generated TA MPC850 Family User’s Manual...
Page 579: Peripheral Write, Internally-Generated Ta
IDMA Emulation CLKOUT Address SETUP HOLD Data SDACK DELAY PHOLD Figure 19-11. SDACK Timing Diagram: Single-Address Peripheral Write, Internally-Generated TA • Single-address memory-write/peripheral-read—The source device is controlled by the IDMA handshake signals (DREQ and SDACK). When the source device requests service from the IDMA channel, IDMA asserts SDACK to allow the source device to drive data onto the data bus.
Page 580: Single-Buffer Mode On Idma1—A Special Case
Single-buffer mode is selected by setting RCCR[EIE], the CPM external interrupt enable bit; see Section 18.5.1, “RISC Controller Conﬁguration Register (RCCR).” Note that the CPM external interrupt always refers to a special request to the CPM, not to the core. MPC850 Family User’s Manual...
Page 581: Idma1 Channel Mode Register (Dcmr) (Single-Buffer Mode)
IDMA Emulation 19.3.9.1 IDMA1 Channel Mode Register (DCMR) (Single-Buffer Mode) DCMR contains the channel’s function code and byte-order convention, previously held in function code registers. DCMR also holds the channel start bit (enable) and burst transfer information. Figure 19-13 shows the DCMR format. AT[1–3] Field —...
Page 582: Idma1 Mask Register (Idmr1) (Single-Buffer Mode)
The peripheral must negate DREQ0 before the last beat of the transfer; otherwise, IDMA assumes that another DMA request is pending—DCMR[STR] will not be cleared—and immediately initiates another transfer. If no buffer is available when this extra transfer begins, erratic operation occurs. MPC850 Family User’s Manual...
Page 583: External Recognition Of An Idma Transfer
IDMA Emulation CLKOUT GCLK1 A[0:31] Column 1 Column 2 Column 3 Column 4 D[0:31] CS1 (RAS) BS[0:3] (CAS[0:3]) BDIP SDACK1 DREQ0 Figure 19-15. Single-Address IDMA1 Burst Timing (Single-Buffer Mode) 19.3.10 External Recognition of an IDMA Transfer The following are ways to externally determine if IDMA is executing a bus cycle: •...
Page 584: Interrupts During An Idma Bus Transfer
IDMA Emulation 19.3.11 Interrupts During an IDMA Bus Transfer The MPC850 supports a synchronous bus structure with provisions allowing a bus master to detect and respond to errors during a bus cycle. An IDMA channel recognizes the same bus interrupt sources that the core recognizes—reset and transfer error acknowledge (TEA).
Page 585 Chapter 20 Serial Interface The physical interface to the SCCs and SMCs is implemented in the serial interface (SI). The SI allows each individual SCC and SMC to be connected externally either through a time-division multiplexed (TDM) interface or through dedicated pins in a non-multiplexed serial interface (NMSI).
Page 586: Si Features
TDMa/SMC2 Non-multiplexed Serial Interface (NMSI) Strobes Pins Pins Figure 20-1. MPC850 SI Block Diagram 20.1 SI Features The TSA’s main features are as follows: • Ability to connect the TDM channel as follows: — T1 or CEPT line — Pulse code modulation highway (PCM) —...
Page 587: The Time-Slot Assigner (Tsa)
The Time-Slot Assigner (TSA) — ISDN basic rate—using an interchip digital link (IDL) — ISDN basic rate—using a general circuit interface (GCI) — User-deﬁned interfaces • Independent Tx and Rx routing paths programmed in the SI RAM • Independent Tx and Rx frame syncs •...
Page 588 8 bits or even to a single contiguous position within the frame. For more ﬂexibility, the user can also provide separate Rx and Tx syncs as well as independent clocks. Figure 20-2 shows example TSA conﬁgurations ranging from the simplest to the most complex. MPC850 Family User’s Manual...
Page 589 The Time-Slot Assigner (TSA) Simplest TDM Example MPC850 1 TDM Sync 1 TDM Clk SCC2 SMC1 Slot n TDM Tx Slot 3 Slot n TDM Rx Slot 3 SCC2 SMC1 More Complex TDM Example – Unique Routing MPC850 1 TDM Sync...
Page 590 Note that a sync pulse received during TSA frame routing is ignored. However, when programmed for a one-clock delay between the sync and start-of-frame pulses, the TSA can accept the last bit of a frame overlapping the sync pulse of the next frame. MPC850 Family User’s Manual...
Page 591: Tsa Signals
20.2.1 TSA Signals The TSA signals for TDMa are shown in Table 20-1. Table 20-1. TSA Signals Signal Description L1RSYNCa/L1TSYNCa Receive/transmit synchronization signals. Input to the MPC850. L1RCLKa/L1TCLKa Receive/transmit clocks. Input to the MPC850. L1RXDa Receive data. Input to the MPC850. L1TXDa Transmit data.
Page 592: Si Ram
20.2.3.3 SI RAM Dynamic Changes The routing of a TDM channel can be changed while the SCCs and SMCs remain connected to the TSA. Enabling dynamic changes divides the SI RAM into current-route and work-space shadow areas. MPC850 Family User’s Manual...
Page 593 The Time-Slot Assigner (TSA) Once the current-route RAM is programmed, the TDM channel can be enabled and SI operation begun. New routing information can then be programmed into the shadow RAM. Setting the channel’s change-shadow-RAM bits, SICMR[CSRRa, CSRTa], in the SI command register tells the SI to activate the shadow RAM (deactivating the current-route RAM) when the next frame sync arrives.
Page 594: Tdma Channel With Dynamic Frames
20.2.3.4 TDMa Channel with Dynamic Frames In an SI conﬁguration using the one TDM channel with dynamic frames, TDMa has 32 entries apiece for Tx and Rx data/strobe routing, as shown in Figure 20-6. One RAM MPC850 Family User’s Manual...
Page 595: Programming The Si Ram
The Time-Slot Assigner (TSA) partition is the current-route RAM; the other is shadow RAM that can be safely reprogrammed. After programming the shadow RAM, set the CSRa bit of the channel in the SI command register (SICMR). When the next frame sync arrives, the SI swaps the current-route RAM with the shadow RAM.
Page 596 Figure 20-8. Example Using SI RAMn[SWTR] The SWTR option allows station B to listen to transmissions from and send data to station A. By setting SWTR in its Rx route RAM entry, station B receives data from L1TXD and, MPC850 Family User’s Manual...
Page 597: Si Ram Programming Example
The Time-Slot Assigner (TSA) if the time slot’s Tx route RAM entry allows, sends data on L1RXD. To prevent sending on L1RXD while listening to station A, clear the CSEL bits in the corresponding Tx route RAM entries. Conversely, to prevent receiving on L1TXD while sending on L1RXD, clear the CSEL bits in corresponding Rx SI RAM entries.
Page 598: The Si Registers
SCC. 20.2.4.2 SI Mode Register (SIMODE) The SI mode register (SIMODE), shown in Figure 20-10, deﬁnes the SI operation modes for the TDM channel and SMCs. MPC850 Family User’s Manual...
Page 599 The Time-Slot Assigner (TSA) Field SMC2 SMC2CS — Reset Addr 0xAE0 Field SMC1 SMC1CS SDMa RFSDa DSCa CRTa STZa CEa FEa GMa TFSDa Reset Addr 0xAE2 Figure 20-10. SI Mode Register (SIMODE) Table 20-5 describes the SIMODE ﬁelds. Table 20-5. SIMODE Field Descriptions Bits Name Description...
Page 600 Tx frame. If CRTa is set, the Rx sync is used as the common sync, and the TFSDa bits refer to this common sync. 00 No bit delay. The ﬁrst bit of the frame is sent on the same clock as the sync. 01 1-bit delay. 10 2-bit delay. 11 3-bit delay. MPC850 Family User’s Manual...
Page 601 The Time-Slot Assigner (TSA) The following series of ﬁgures show timing examples. Figure 20-11 and Figure 20-12 show the effects of changing the delay from frame sync to data valid. L1CLK (CE=0) End of Frame L1SYNC (FE=1) Data Bit-0 Bit-1 Bit-2 Bit-3 Bit-4...
Page 602 Both the FE Settings (On Bit-0) Rx Sampled Here Figure 20-14. Falling Edge (FE) Effect When CE = 0 and xFSD = 01 Figure 20-15 shows SIMODE[FE] behavior with SIMODE[CE] set and no frame sync delay. MPC850 Family User’s Manual...
Page 603 The Time-Slot Assigner (TSA) CE=1 xFSD=00 L1CLK L1SYNC (FE=0) L1TXD (Bit-0) The L1ST is Driven from Sync. L1ST Data is Driven from Clock Low. (On Bit-0) Rx Sampled Here L1SYNC (FE=0) L1TXD (Bit-0) L1ST is Driven from Clock High. L1ST (On Bit-0) L1SYNC (FE=1)
Page 604: Si Clock Route Register (Sicr)
The SI clock route register (SICR), shown in Figure 20-17, selects the SCC clock source from one of four baud rate generators or an input from the bank of clock pins. The SICR also connects the SCCs to the TSA and enables the grant mechanism chosen in SIMODE. MPC850 Family User’s Manual...
Page 605 The Time-Slot Assigner (TSA) Bits Field — GR3 SC3 R3CS T3CS Reset Addr 0xAEC Bits Field GR2 SC2 R2CS T2CS — R1CS — Reset Addr 0xAEE Figure 20-17. SI Clock Route Register (SICR) Table 20-6 describes the SICR ﬁelds. Table 20-6. SICR Field Descriptions Bits Name Description...
Page 606: Si Command Register (Sicmr)
Table 20-8 describes the SISTR ﬁelds. Table 20-8. SISTR Field Descriptions Bits Name Description CRORa Address of the current route of TDMa receiver. 0 Address 0–127 when SIGMR[RDM] = 01. 1 Address 128–255 when SIGMR[RDM] = 01. MPC850 Family User’s Manual...
Page 607: Si Ram Pointer Register (Sirp)
The Time-Slot Assigner (TSA) Table 20-8. SISTR Field Descriptions (Continued) Bits Name Description CROTa Address of the current route of TDMa transmitter. 0 Address 256–383 when SIGMR[RDM] = 01. 1 Address 384–511 when SIGMR[RDM] = 01. 2–7 — Reserved, should be cleared. 20.2.4.6 SI RAM Pointer Register (SIRP) The SI RAM pointer (SIRP) register, shown in Figure 20-20, indicates the RAM entry currently being serviced.
Page 608: Idl Bus Implementation
The full-duplex ISDN interchip digital link (IDL) interface connects a physical layer device to the MPC850. The basic and primary rate of the IDL bus is supported by the MPC850. In the basic rate, data on three channels (B1, B2, and D) is transferred in a 20-bit frame, providing a full-duplex bandwidth of 160 Kbps.
Page 609: Isdn Terminal Adaptor Application
Transceiver Figure 20-22. ISDN Terminal Adaptor Using IDL The MPC850 can identify and support each IDL channel or it can output strobe lines for interfacing with devices that do not support the IDL bus. The IDL signals for each transmit and receive channel are as follows: •...
Page 610 The Time-Slot Assigner (TSA) • L1RXDa—IDL receive data. Input to the MPC850. Valid only for bits supported by the IDL; ignored for other signals that may be present. • L1TXDa—IDL transmit data. Output from the MPC850. Valid only for bits supported by the IDL;...
Page 611: Programming The Idl Interface
L1GRa when the IDL sync signal (L1RSYNCa) is asserted. If L1GRa is asserted, the MPC850 sends the ﬁrst zero of the opening ﬂag in the ﬁrst bit of the D channel. If a collision is detected on the D channel, the physical layer device negates L1GRa. The MPC850 then stops its transmission and resends the frame when L1GRa is reasserted.
Page 612: Gci Bus Implementation
SCC2 and SMC2 as needed. 20.2.6 GCI Bus Implementation The MPC850 fully supports both the normal mode (also known as ISDN-oriented modular rev 2.2 (IOM-2)) and the SCIT mode of the general circuit interface (GCI). It also supports the D channel access control in S/T interface terminals by using the command/indication (C/I) channel.
Page 613 In the GCI bus, the clock rate is twice the data rate. The SI divides the input clock by two to produce the data clock. The MPC850 also has data strobe lines used as an interface for devices that do not support the GCI bus. Shown in Figure 20-24, the GCI signals for each Tx and Rx channel are as follows: •...
Page 614: Gci Activation/Deactivation
The MPC850 supports contention detection on the D channel of the SCIT bus. When the MPC850 has data to send on the D channel, it checks an SCIT bus bit that is marked with a special route code (usually, bit 4 of C/I channel 2). The physical layer device monitors the physical layer bus for activity on the D channel and indicates on this bit that the channel is free.
Page 615: Gci Interface (Scit Mode) Programming Example
The Time-Slot Assigner (TSA) to the supporting SCC. The received bit (grant) should be marked by programming the CSEL (channel select) bits of the SI RAM to 0b111 for an internal assertion of a strobe. This bit is sampled by the SI and transferred to the D-channel SCC as the grant. The grant is generally bit 4 of the C/I in channel 2 of the GCI bus, but any bit slot can be selected in the SI RAM.
Page 616 SCC or SMC. These names do not correspond to physical pins on the MPC850. Note the internal RCLKx and TCLKx can be used as inputs to the DPLL unit, which is inside the SCCx; thus, RCLKx and TCLKx are not always required to reﬂect the actual bit rate on the line.
Page 617 NMSI Conﬁguration BRG1 BRG2 BRG3 BRG4 BRGO1 BRGO2 BRGO3 SCC3 RCLK3 TCLK3 SCC3 CLK1 SCC2 RCLK2 CLK2 TCLK2 SCC2 Bank of Clocks Selection Logic CLK3 USBCLK CLK4 SMC1 SMCLK1 SCCs and USBCLK controlled in SICR. SMCLK2 SMCs controlled in SIMODE. SMC2 Figure 20-25.
Page 618: Baud Rate Generators (Brgs)
• A 16x divider option allows slow baud rates at high system frequencies • Each BRG contains an autobaud support option • Each BRG output (except BRG4) can be routed to a pin (BRGOn) Figure 20-26 shows a baud rate generator. MPC850 Family User’s Manual...
Page 619 Figure 20-26. Baud Rate Generator (BRG) Block Diagram The BRG clock source can be BRGCLK, CLK2, or CLK4 (selected in BRGCn[EXTC]). The BRGCLK is generated in the MPC850 clock synthesizer speciﬁcally for the BRGs, the SPI, and the I C internal baud rate generator. Alternatively, the CLK2 and CLK4 pins can be conﬁgured as clock sources.
Page 620: Baud Rate Generator Configuration Registers (Brgcn)
0 Stop all clocks to the BRG. 1 Enable clocks to the BRG. 16–17 EXTC External clock source. Selects the BRG input clock. 00 BRGCLK (internal clock generated by the clock synthesizer in the SIU). 01 CLK2 10 CLK4 11 Reserved. MPC850 Family User’s Manual...
Page 621: Autobaud Operation On The Scc Uart
Baud Rate Generators (BRGs) Table 20-13. BRGCn Field Descriptions (Continued) Bits Name Description Autobaud. Selects autobaud operation for BRGn on the corresponding RXDn. ATB must remain zero until the SCC receives the three Rx clocks. Then the user must set ATB to obtain the correct baud rate. After the baud rate is obtained and locked, it is indicated by setting AB in the UART event register.
Page 622: Uart Baud Rate Examples
1301 1279 149.954 300.48 300.5 2082 600.09 2603 2559 1200 1040 1200.7 1301 1200 1279 1200 2400 2399.2 2400.1 2400 4800 4807.7 4807.69 4800 9600 9615.4 9585.9 9600 19200 19231 19290 19200 38400 37879 38109 38400 MPC850 Family User’s Manual...
Page 623 Baud Rate Generators (BRGs) Table 20-14. Typical Baud Rates for Asynchronous Communication (Continued) System Frequency Baud 20 MHz 25 MHz 24.5760 MHz Rate Div16 Actual Frequency Div16 Actual Frequency Div16 Actual Frequency 57600 56818 57870 56889 115200 113636 111607 118154 For synchronous communication, the internal clock is identical to the baud rate output.
Page 624 Baud Rate Generators (BRGs) MPC850 Family User’s Manual...
Page 625: Scc Transparent Mode
Chapter 21 Serial Communications Controllers The MPC850 has two serial communications controllers (SCCs), which can be conﬁgured independently to implement different protocols for bridging functions, routers, and gateways, and to interface with a wide variety of standard WANs, LANs, and proprietary networks.
Page 626: Features
DPLL can be disabled, in which case only NRZ and NRZI are supported. An SCC can be connected to its own set of pins on the MPC850. This conﬁguration is called the non-multiplexed serial interface (NMSI) and is described in Chapter 20, “Serial Interface.”...
Page 627: Scc Registers
The SCCs are the same on both the MPC850 and MPC860, except that the MPC850’s SCC2 supports a wider range of IrDA signaling rates. Note also that the MPC850 SCCs do not support the external CAM for the Ethernet/IEEE 802.3 protocol.
Page 628 For full-duplex totally transparent operation, set both TTX and TRX. Note that an SCC cannot operate half in Ethernet or serial ATM mode and half in transparent mode. For example, if MODE = 0b1100 (Ethernet), erratic operation occurs unless TTX = TRX. MPC850 Family User’s Manual...
Page 629 1 CD/CTS is assumed to be synchronous with data, which speeds up operation. CD or CTS must transition while the Rx/Tx clock is low, at which time, the transfer begins. Useful for connecting MPC850 in transparent mode since the RTS of one MPC850 can connect directly to the CD/CTS of another.
Page 630 Tx clock can be latched by the external receiver one clock cycle later on the next rising edge of the same Tx clock. Recommended for Ethernet, HDLC, and transparent operation when clock rates exceed 8 MHz to improve data setup time for the external transceiver. MPC850 Family User’s Manual...
Page 631 SCC Registers Table 21-2. GSMR_L Field Descriptions (Continued) Name Description 4–5 TSNC Transmit sense. Determines the amount of time the internal carrier sense signal stays active after the last transition on RXD, indicating that the line is free. For instance, AppleTalk can use TSNC to avoid a spurious CS-changed (SCCE[DCC]) interrupt that would otherwise occur during the frame sync sequence before the opening ﬂags.
Page 632 ENR can be set or cleared, regardless of whether serial clocks are present. Section 21.4.7, “Reconﬁguring the SCCs,” describes how to disable/enable the SCCs. Note also these other tools provided for controlling SCC reception: the commands, and ENTER HUNT MODE CLOSE RXBD RxBD[E]. MPC850 Family User’s Manual...
Page 633: Data Synchronization Register (Dsr)
SCC Registers Table 21-2. GSMR_L Field Descriptions (Continued) Name Description Enable transmit. Enables the transmitter hardware state machine for the SCC. 0 The transmitter is disabled. If ENT is cleared during transmission, the current character is aborted and TXD returns to the idle state. Data already in the Tx shift register is not sent. 1 The transmitter is enabled.
Page 634: Transmit-On-Demand Register (Todr)
TxBDs are added to the BD table as long as older TxBDs are still being processed. New TxBDs are processed in order. The ﬁrst bit of the frame is typically clocked out 5-6 bit times after TOD is set. 1–15 — Reserved, should be cleared. MPC850 Family User’s Manual...
Page 635: Scc Buffer Descriptors (Bds)
SCC Buffer Descriptors (BDs) 21.3 SCC Buffer Descriptors (BDs) Data associated with each SCC is stored in buffers and each buffer is referenced by a buffer descriptor (BD) that can reside anywhere in dual-port RAM. The total number of 8-byte BDs is limited only by the size of the dual-port RAM (128 BDs/1 Kbyte).
Page 636 The buffer is then closed; subsequent data uses the next BD. If E = 0, the current buffer is not empty MPC850 Family User’s Manual...
Page 637: Scc Parameter Ram
SCC Parameter RAM and it reports a busy error. The CP does not move from the current BD until E is set by the core (the buffer is empty). After using a descriptor, the CP clears E (not empty) and does not reuse a BD until it has been processed by the core.
Page 638 Protocol-speciﬁc area. (The size of this area depends on the protocol chosen.) From SCC base. SCC base = IMMR + 0x3D00 (SCC2) or 0x3E00 (SCC3) These parameters need not be accessed for normal operation but may be helpful for debugging. For CP use only MPC850 Family User’s Manual...
Page 639: Handling Scc Interrupts
SCC Parameter RAM 21.4.1 Function Code Registers (RFCR and TFCR) Each SCC has two separate function code registers—one for Rx buffers (RFCRx) and one for Tx buffers (TFCRx). Function code registers contain the value to appear on AT[1–3] when the associated SDMA channel accesses memory. It also selects the byte-ordering convention.
Page 640: Scc Initialization
Regardless of the protocol used, follow these steps: 1. Write the parallel I/O ports to conﬁgure and connect the I/O pins to the SCC. 2. Set the SDMA conﬁguration register SDCR[RAID] ﬁeld to 0b01 (U-bus arbitration priority level 5). MPC850 Family User’s Manual...
Page 641: Controlling Scc Timing With Rts, Cts, And Cd
SCC Parameter RAM 3. Conﬁgure the parallel I/O registers to enable RTS, CTS, and CD if these signals are required. 4. If the time-slot assigner (TSA) is used, the serial interface (SI) must be conﬁgured. If the SCC is used in NMSI mode, SICR must still be initialized. 5.
Page 642 CTS lost error. Negating CTS forces RTS high and Tx data to become idle. If GSMR_H[CTSS] is zero, the SCC must sample CTS before a CTS lost is recognized; otherwise, the negation of CTS immediately causes the CTS lost condition. See Figure 21-11. MPC850 Family User’s Manual...
Page 643 SCC Parameter RAM TCLK Data Forced High (Output) First Bit of Frame Data RTS Forced High (Output) CTS Sampled Low Here CTS Sampled High Here (Input) CTS Lost Signaled in Frame BD NOTE 1. GSMR_H[CTSS] = 0. CTSP=0 or no CTS lost can occur. TCLK Data Forced High (Output)
Page 644: Asynchronous Protocols
• If CTS is not already asserted when RTS is asserted and GSMR_H[CTSS] = 0, transmission begins in three additional bit times. • If CTS is not already asserted when RTS is asserted and GSMR_H[CTSS] = 1, transmission begins in two additional bit times. MPC850 Family User’s Manual...
Page 645: Digital Phase-Locked Loop (Dpll) Operation
SCC Parameter RAM 21.4.5 Digital Phase-Locked Loop (DPLL) Operation Each SCC includes a digital phase-locked loop (DPLL) for recovering clock information from a received data stream. For applications that provide a direct clock source to the SCC, the DPLL can be bypassed by selecting 1x mode for GSMR_L[RDCR, TDCR]. If the DPLL is bypassed, only NRZ or NRZI encodings are available.
Page 646 DPLL should receive a preamble pattern before it receives the data. In some protocols, the preceding ﬂags or syncs can function as a preamble; others use the patterns in Table 21-7. When transmission occurs, the SCC can generate preamble patterns, as programmed in GSMR_L[TPP, TPL]. MPC850 Family User’s Manual...
Page 647: Encoding Data With A Dpll
CLKx or generated by an internal baud rate generator may be up to 25 MHz on a 25-MHz MPC850, if the DPLL 8×, 16×, or 32× option is used. Note the 1:2 system clock/serial clock ratio does not apply when the DPLL is used to recover the clock in the 8×, 16×, or 32×...
Page 648: Clock Glitch Detection
21.4.6 Clock Glitch Detection Clock glitches cause problems for many communications systems, and they may go undetected by the system. Systems that supply an external clock to a serial channel are often MPC850 Family User’s Manual...
Page 649 The SCCs on the MPC850 have a special circuit designed to detect glitches and alert the system of a problem at the physical layer. The glitch-detect circuit is not a speciﬁcation test;...
Page 650: Reset Sequence For An Scc Transmitter
Tx and Rx parameters. RX PARAMETERS 3. Set GSMR_L[ENT, ENR] to enable the SCC with the new protocol. 21.4.8 Saving Power To save power when not in use, an SCC can be disabled by clearing GSMR_L[ENT, ENR]. MPC850 Family User’s Manual...
Page 651: Scc Uart Mode
Chapter 22 SCC UART Mode The universal asynchronous receiver transmitter (UART) protocol is commonly used to send low-speed data between devices. The term asynchronous is used because it is not necessary to send clocking information along with the data being sent. UART links are typically 38400 baud or less and are character-based.
Page 652: Features
• Received break character length indication • Programmable data length (5–8 bits) • Programmable fractional stop bit lengths (from 9/16 to 2 bits) in transmission • Capable of reception without a stop bit • Even/odd/force/no parity generation and check MPC850 Family User’s Manual...
Page 653: Normal Asynchronous Mode
Normal Asynchronous Mode • Frame error, noise error, break, and idle detection • Transmit preamble and break sequences • Freeze transmission option with low-latency stop 22.2 Normal Asynchronous Mode In normal asynchronous mode, the receive shift register receives incoming data on RXD. Control bits in the UART mode register (PSMR) deﬁne the length and format of the UART character.
Page 654: Scc Uart Parameter Ram
Transmit out-of-sequence character. Inserts out-of-sequence characters, such as XOFF and XON, into the transmit stream. The TOSEQ character is put in the Tx FIFO without affecting a Tx buffer in progress. See Section 22.11, “Inserting Control Characters into the Transmit Data Stream.” MPC850 Family User’s Manual...
Page 655: Data-Handling Methods: Character- Or Message-Based
Data-Handling Methods: Character- or Message-Based Table 22-1. UART-Specific SCC Parameter RAM Memory Map (Continued) 0x50 CHARACTER1 Hword Control character 1–8. These characters deﬁne the Rx control characters on which interrupts can be generated. CHARACTER2 0x52 Hword CHARACTER3 0x54 Hword CHARACTER4 0x56 Hword 0x58...
Page 656: Error And Status Reporting
Resets the receive parameters in the parameter RAM. Should be issued when the receiver is disabled. INIT RX Note that resets both Tx and Rx parameters. PARAMETERS INIT TX AND RX PARAMETERS MPC850 Family User’s Manual...
Page 657: Multidrop Systems And Address Recognition
Multidrop Systems and Address Recognition 22.8 Multidrop Systems and Address Recognition In multidrop systems, more than two stations can be on a network, each with a speciﬁc address. Figure 22-2 shows two examples of this conﬁguration. Frames made up of many characters can be broadcast as long as the ﬁrst character is the destination address.
Page 658 CHARACTERn. Each RCCM bit corresponds to the respective bit of CHARACTERn and decodes as follows. 0 Ignore this bit when comparing the incoming character to CHARACTERn. 1 Use this bit when comparing the incoming character to CHARACTERn. MPC850 Family User’s Manual...
Page 659: Hunt Mode (Receiver)
Hunt Mode (Receiver) Table 22-4. Control Character Table, RCCM, and RCCR Descriptions (Continued) Offset Bits Name Description 0x62 0–7 — Reserved 8–15 RCCR Received control character register. If the newly arrived character matches and is rejected from the buffer (R = 1), the PIP controller writes the character into the RCCR and generates a maskable interrupt.
Page 660: Sending A Break (Transmitter)
FSB ﬁeld in the data synchronization register (DSR) determines the fractional length of the last stop bit to be sent. FSB can be modiﬁed at any time. If two stop bits are sent, only the second is affected. Idle characters are always sent as full-length characters. MPC850 Family User’s Manual...
Page 661: Handling Errors In The Scc Uart Controller
Handling Errors in the SCC UART Controller Field — — — — — — — — — — — — Reset Addr 0xA2E (DSR2), 0xA4E (DSR3) Figure 22-5. Data Synchronization Register (DSR) Table 22-6 describes DSR ﬁelds. Table 22-6. DSR Fields Descriptions Name Description —...
Page 662: Uart Mode Register (Psmr)
22.16 UART Mode Register (PSMR) For UART mode, the SCC protocol-speciﬁc mode register (PSMR) is called the UART mode register. Many bits can be modiﬁed while the receiver and transmitter are enabled. MPC850 Family User’s Manual...
Page 663 UART Mode Register (PSMR) Figure 22-6 shows the PSMR in UART mode. Field FRZ RZS SYN DRT — Reset Addr 0xA28 (PSMR2), 0xA48 (PSMR3) Figure 22-6. Protocol-Specific Mode Register for UART (PSMR) Table 22-9 describes PSMR UART ﬁelds. Table 22-9. PSMR UART Field Descriptions Name Description Flow control.
Page 664: Scc Uart Receive Buffer Descriptor (Rxbd)
• A MAX_IDL number of consecutive idle characters is received. • An command is issued. ENTER HUNT MODE CLOSE RXBD • An address character is received in multidrop mode. The address character is written to the next buffer for a software comparison. MPC850 Family User’s Manual...
Page 665 SCC UART Receive Buffer Descriptor (RxBD) Figure 22-7 shows an example of how RxBDs are used in receiving. MRBLR = 8 Bytes for the SCC Rx BD 0 Buffer Status Byte 1 Length 0008 Byte 2 Buffer Full Pointer 32-Bit Buffer Pointer 8 Bytes etc.
Page 666 0 The address matched the value in UADDR2. 1 The address matched the value in UADDR1. — Reserved, should be cleared. Break received. Set when a break sequence is received as data is being received into this buffer. MPC850 Family User’s Manual...
Page 667: Scc Uart Transmit Buffer Descriptor (Txbd)
SCC UART Transmit Buffer Descriptor (TxBD) Table 22-10. SCC UART RxBD Status and Control Field Descriptions (Continued) Bits Name Description Framing error. Set when a character with a framing error (a character without a stop bit) is received and located in the last byte of this buffer. A new Rx buffer is used to receive subsequent data. Parity error.
Page 668: Scc Uart Event Register (Scce) And Mask Register (Sccm)
SCCE bit. Interrupts can be masked in the UART mask register (SCCM), which has the same format as SCCE. Setting a mask bit enables the corresponding SCCE interrupt; clearing a bit masks it. Figure 22-10 shows example interrupts that can be generated by the SCC UART controller. MPC850 Family User’s Manual...
Page 669 SCC UART Event Register (SCCE) and Mask Register (SCCM) Characters Received by UART 10 Characters Time Line Idle Line Idle Break UART SCCE IDL BRKS BRKE IDL CD Events Notes: 1. The first RX event assumes Rx buffers are 6 bytes each. 2.
Page 670: Scc Uart Status Register (Sccs)
RXD. The real-time status of CTS and CD is part of the port C parallel I/O. Field — Reset 0000_0000_0000_0000 Addr 0xA37 (SCCS2), 0xA57 (SCCS3) Figure 22-12. SCC Status Register for UART Mode (SCCS) MPC850 Family User’s Manual...
Page 671: Scc Uart Programming Example
SCC UART Programming Example Table 22-13 describes UART SCCS ﬁelds. Table 22-13. UART SCCS Field Descriptions Bits Name Description 0–6 — Reserved, should be cleared. Idle status. Set when RXD has been a logic one for at least a full character time. 0 The line is not idle.
Page 672: S-Records Loader Application
S-record ﬁts into a single buffer. Follow the basic UART initialization sequence above in Section 22.21, “SCC UART Programming Example,” except allow for more and larger buffers and create the control character table as described in Table 22-14. MPC850 Family User’s Manual...
Page 673 S-Records Loader Application Table 22-14. UART Control Characters for S-Records Example Character Description Line Feed Both the E and R bits should be cleared. When an end-of-line character is received, the current buffer is closed and made available to the core for processing. This buffer contains an entire S record that the processor can now check and copy to memory or disk as required.
Page 674 S-Records Loader Application MPC850 Family User’s Manual...
Page 675 Chapter 23 SCC HDLC Mode HDLC (high-level data link control) is one of the most common protocols in the data link layer, layer 2 of the OSI model. Many other common layer 2 protocols, such as SDLC, SS#7, AppleTalk, LAPB, and LAPD, are based on HDLC and its framing structure in particular.
Page 676: Scc Hdlc Features
TxBD[R] is cleared. Before the SCC proceeds to the next TxBD in the table, an interrupt can be issued if TxBD[I] is set. This interrupt programmability allows the core to intervene after each buffer, after a speciﬁc buffer, or after each frame. MPC850 Family User’s Manual...
Page 677: Scc Hdlc Channel Frame Reception
SCC HDLC Channel Frame Reception command can be used to expedite critical data ahead of previously STOP TRANSMIT linked buffers or to support efﬁcient error handling. When the SCC receives a STOP command, it sends idles or ﬂags instead of the current frame until it receives a TRANSMIT command.
Page 678 0xFFFF. For 8-bit addresses, clear the eight high-order HMASK bits. See Figure 23-2. 0x58 Hword Temporary storage. 0x5A TMP_MB Hword Temporary storage. From SCC base. SCC base = IMMR + 0x3D00 (SCC2) or 0x3E00 (SCC3) MPC850 Family User’s Manual...
Page 679: Programming The Scc Hdlc Controller
Programming the SCC HDLC Controller Figure 23-2 shows 16- and 8-bit address recognition. 16-Bit Address Recognition 8-Bit Address Recognition Flag Address Address Control Flag Address Control etc. etc. 0x7E 0x68 0xAA 0x44 0x7E 0x55 0x44 HMASK 0xFFFF HMASK 0x00FF HADDR1 0xAA68 HADDR1 0xXX55...
Page 680: Handling Errors In The Scc Hdlc Controller
Highest priority error. The channel stops frame reception, closes the buffer, sets RxBD[CD], and during generates the RXF interrupt if not masked. The rest of the frame is lost and other errors are not Frame checked in that frame. At this point, the receiver enters hunt mode. Reception MPC850 Family User’s Manual...
Page 681: Hdlc Mode Register (Psmr)
HDLC Mode Register (PSMR) Table 23-5. Receive Errors (Continued) Error Description Abort Occurs when seven or more consecutive ones are received. When this occurs while receiving a Sequence frame, the channel closes the buffer, sets RxBD[AB] and generates a maskable RXF interrupt. The channel also increments the abort sequence counter ABTSC.
Page 682: Scc Hdlc Receive Buffer Descriptor (Rxbd)
The CPM uses the RxBD, shown in Figure 23-4, to report on data received for each buffer. Offset + 0 — — — Offset + 2 Data Length Offset + 4 Rx Buffer Pointer Offset + 6 Figure 23-4. SCC HDLC Receive Buffer Descriptor (RxBD) MPC850 Family User’s Manual...
Page 683 SCC HDLC Receive Buffer Descriptor (RxBD) Table 23-7 describes HDLC RxBD status and control ﬁelds. Table 23-7. SCC HDLC RxBD Status and Control Field Descriptions Bits Name Description Empty. 0 The buffer is full or reception stopped because of an error. The core can read or write to any ﬁelds of this RxBD.
Page 684 Unexpected Abort Present Time Occurs before Time Legend: Closing Flag F = Flag A = Address Byte C = Control Byte I = Information Byte CR = CRC Byte Figure 23-5. SCC HDLC Receiving using RxBDs MPC850 Family User’s Manual...
Page 685: Scc Hdlc Transmit Buffer Descriptor (Txbd)
SCC HDLC Transmit Buffer Descriptor (TxBD) 23.10 SCC HDLC Transmit Buffer Descriptor (TxBD) The CPM uses the TxBD, shown in Figure 23-6, to conﬁrm transmissions and indicate error conditions. Offset + 0 — — Data Length Offset + 2 Tx Buffer Pointer Offset + 4 Offset + 6 Figure 23-6.
Page 686: Hdlc Event Register (Scce)/Hdlc Mask Register (Sccm)
It is set no sooner than two clocks after the last bit of the closing ﬂag is received. This event is not maskable via the RxBD[I] bit. Busy condition. Indicates a frame arrived but was discarded due to a lack of buffers. MPC850 Family User’s Manual...
Page 687: Hdlc Event Register (Scce)/Hdlc Mask Register (Sccm)
HDLC Event Register (SCCE)/HDLC Mask Register (SCCM) Table 23-9. SCCE/SCCM Field Descriptions (Continued) Bits Name Description Transmit buffer. Enabled by setting TxBD[I]. TXB is set when a buffer is sent on the HDLC channel. For the last buffer in the frame, TXB is not set before the last bit of the closing ﬂag begins its transmission; otherwise, it is set after the last byte of the buffer is written to the Tx FIFO.
Page 688: Scc Hdlc Status Register (Sccs)
The following initialization sequence is for an SCC HDLC channel with an external clock. SCC2 is used with RTS2, CTS2, and CD2 active; CLK3 is used for both the HDLC receiver and transmitter. 1. Conﬁgure port A to enable TXD2 and RXD2. Set PAPAR[12,13] and clear PADIR[12,13] and PAODR[12,13]. MPC850 Family User’s Manual...
Page 689 SCC HDLC Programming Examples 2. Conﬁgure port C to enable RTS2, CTS2, and CD2. Set PCPAR[14] and PCSO[8,9] and clear PCPAR[8,9] and PCDIR[8,9,14]. 3. Conﬁgure port A to enable CLK3. Set PAPAR[5] and clear PADIR[5]. 4. Connect CLK3 to SCC2 using the SI. Write 0b110 to SICR[R2CS] and SICR[T2CS].
Page 690: Scc Hdlc Programming Example #2
LAN and point-to-multipoint conﬁgurations. Review the basic features of the I.430 and T1.605 before learning about the HDLC bus. The I.430 and T1.605 deﬁne a way to connect eight terminals over the D-channel of the S/T MPC850 Family User’s Manual...
Page 691 HDLC Bus Mode with Collision Detection ISDN bus. The layer 2 protocol is a variant of HDLC, called LAPD. However, at layer 1, a method is provided to allow the eight terminals to send frames to the switch through the physical S/T bus.
Page 692 2. The TXD pins of slave devices should be configured to open-drain in the port C parallel I/O port. 3. Clock1 is the master RCLK and the slave TCLK. 4. Clock2 is the master TCLK and the slave RCLK. Figure 23-11. Typical HDLC Bus Single-Master Configuration MPC850 Family User’s Manual...
Page 693: Hdlc Bus Features
HDLC Bus Mode with Collision Detection 23.14.1 HDLC Bus Features The main features of the HDLC bus are as follows: • Superset of the HDLC controller features • Automatic HDLC bus access • Automatic retransmission in case of collision • May be used with the NMSI or a TDM bus •...
Page 694: Increasing Performance
Figure 23-14 shows local HDLC bus controllers using a standard transmission line and a local bus. The controllers do not communicate with each other but with a station on the transmission line; yet the HDLC bus protocol controls access to the transmission line. MPC850 Family User’s Manual...
Page 695 HDLC Bus Mode with Collision Detection + 3.3V Local HDLC Bus Line Driver (1-Bit Delay) HDLC Bus HDLC Bus Controller Controller NOTES: 1. The TXD pins of slave devices should be configured to open-drain in the port C parallel I/O port. 2.
Page 696: Using The Time-Slot Assigner (Tsa)
23.14.6.1 Programming GSMR and PSMR for the HDLC Bus Protocol To program the protocol-speciﬁc mode register (PSMR), set the bits as described below: • Conﬁgure NOF as preferred • Set RTE and BUS to 1 • Set BRM to 1 if delayed RTS is desired MPC850 Family User’s Manual...
Page 697: Hdlc Bus Controller Programming Example
HDLC Bus Mode with Collision Detection • Conﬁgure CRC to 16-bit CRC CCITT (0b00). • Conﬁgure other bits to zero or default. To program the general SCC mode register (GSMR), set the bits as described below: • Set MODE to HDLC mode (0b0000). •...
Page 698 HDLC Bus Mode with Collision Detection MPC850 Family User’s Manual...
Page 699: Operating The Localtalk Bus
LocalTalk physical and link-layer protocol, an HDLC-based protocol that runs at 230.4 kbps. In this manual, the term ‘AppleTalk controller’ assumes the support that the MPC850 provides for LocalTalk protocol. The AppleTalk controller provides required frame synchronization, bit sequence, preamble, and postamble onto standard HDLC frames.
Page 700: Features
• Automatic postamble transmission • Reception of sync sequence does not cause extra SCCE[DCC] interrupts • Reception is automatically disabled while sending a frame • Transmit-on-demand feature expedites frames • Connects directly to an RS-422 transceiver MPC850 Family User’s Manual...
Page 701: Connecting To Appletalk
Connecting to AppleTalk 24.3 Connecting to AppleTalk As shown in Figure 24-2, the MPC850 connects to LocalTalk, and, using TXD, RTS, and RXD, is an interface for the RS-422 transceiver. The RS-422, in turn, is an interface for the LocalTalk connector. Although it is not shown, a passive RC circuit is recommended between the transceiver and connector.
Page 702: Programming The Psmr
Use the transmit-on-demand (TODR) register to expedite a transmit frame. See Section 21.2.4, “Transmit-on-Demand Register (TODR).” 24.4.4 SCC AppleTalk Programming Example Except for the previously discussed register programming, use the example in Section 23.13.1, “SCC HDLC Programming Example #1.” MPC850 Family User’s Manual...
Page 703: Irda Mode—Scc2 Only
HDLC can be implemented in conjunction with the core, it is more efﬁcient and less computationally intensive to let the CPM handle framing and transparency functions. For further information on the implementation of IrDA on the MPC850 see Chapter 29, “IrDA Mode—SCC2 Only.”...
Page 704: Asynchronous Hdlc Frame Transmission Processing
The receiver decodes the transparency character required by asynchronous HDLC protocol as described in Section 25.5, “Receiver Transparency Decoding.” When the frame ends, the controller checks the incoming CRC ﬁeld and writes it to the buffer. The controller then MPC850 Family User’s Manual...
Page 705: Transmitter Transparency Encoding
Transmitter Transparency Encoding updates RxBD[Data Length] with the total frame length, including the CRC bytes. The controller sets RxBD[L], writes the frame status bits, and clears RxBD[E] (if RxBD[CM] is zero). It then sets SCCE[RXF], which indicates that a frame was received and is in memory.
Page 706: Exceptions To Rfc 1549
— Framing error — Break sequence • If an invalid sequence(0x7D7D) is received, the ﬁrst control escape character is discarded, and the second is unconditionally XORed with 0x20. The sequence is thus stored in the buffer as 0x5D. MPC850 Family User’s Manual...
Page 707: Asynchronous Hdlc Channel Implementation
Asynchronous HDLC Channel Implementation 25.7 Asynchronous HDLC Channel Implementation The following points are speciﬁc to asynchronous HDLC channel implementation: • Flag sequence—The transmitter automatically generates the opening and closing ﬂags. The receiver removes opening and closing ﬂags before writing a frame to memory and receives frames with only one shared ﬂag between frames, ignoring multiple ﬂags.
Page 708 25.9 Conﬁguring GSMR and DSR for Asynchronous HDLC General SCC parameters can be conﬁgured as described in Chapter 21, “Serial Communications Controllers,” except for the following changes to the general SCC mode register and the data synchronization register: MPC850 Family User’s Manual...
Page 709: General Scc Mode Register (Gsmr)
Programming the Asynchronous HDLC Controller 25.9.1 General SCC Mode Register (GSMR) Table 25-2 shows asynchronous HDLC-speciﬁc information for the GSMR. Table 25-2. Asynchronous HDLC-Specific GSMR Field Descriptions Name Description Rx FIFO width (GSMR_H[26]) 0 Do not use. 1 Low-latency operation—for character-oriented protocols like UART, BISYNC, and asynchronous HDLC. The Rx FIFO is 8 bits wide and the Rx FIFO is one-fourth its normal size (8 bytes for SCC2;...
Page 710: Handling Errors In The Asynchronous Hdlc Controller
Table 25-5. Transmit Errors Error Description CTS Lost during The channel stops sending the buffer, closes it, sets SCCE[TXE] and TxBD[CT]. The channel Frame resumes sending from the next TxBD after a command is issued. RESTART TRANSMIT Transmission MPC850 Family User’s Manual...
Page 711: Scc Asynchronous Hdlc Registers
SCC Asynchronous HDLC Registers Table 25-6 describes reception errors. Table 25-6. Receive Errors Error Description Overrun SCC2 has 32-byte Rx FIFOs; SCC3 has 16-byte Rx FIFOs. Overrun occurs when the CP cannot keep up with the data rate or the SDMA channel cannot write the received data to memory. The previous data byte and frame status are lost.
Page 712: Scc Asynchronous Hdlc Status Register (Sccs)
RXD. The real-time status of CTS and CD is part of the port C parallel I/O. Field — Reset 0000_0000_0000_0000 Addr 0xA37 (SCCS2), 0xA57 (SCCS3) Figure 25-5. SCC Status Register for Asynchronous HDLC Mode (SCCS) MPC850 Family User’s Manual...
Page 713: Asynchronous Hdlc Mode Register (Psmr)
SCC Asynchronous HDLC RxBDs Table 25-8 describes asynchronous HDLC SCCS ﬁelds. Table 25-8. Asynchronous HDLC SCCS Field Descriptions Bits Name Description 0–6 — Reserved, should be cleared. Idle status. Set when RXD has been a logic one for at least a full character time. 0 The line is not idle.
Page 714 Reserved, should be cleared. Rx abort sequence. Set when an abort sequence or framing error terminates a frame. Rx CRC error. Set when a frame has a CRC error. Received CRC bytes are written to the buffer. MPC850 Family User’s Manual...
Page 715: Scc Asynchronous Hdlc Txbds
SCC Asynchronous HDLC TxBDs Table 25-10. Asynchronous HDLC RxBD Status and Control Field Descriptions (Continued) Bits Name Description Overrun. Set when a receiver overrun occurs during frame reception. Carrier detect lost. Set when CD is negated during frame reception. The data length and buffer pointer ﬁelds are described in Section 21.3, “SCC Buffer Descriptors (BDs).”...
Page 716: Differences Between Hdlc And Asynchronous Hdlc
• The automatic error counters in the HDLC controller are not implemented in the asynchronous HDLC controller. • Noisy characters (characters for which all three samples are not identical) are not accounted for in the asynchronous HDLC controller. It is assumed that the CRC catches any data integrity problems. MPC850 Family User’s Manual...
Page 717: Scc Asynchronous Hdlc Programming Example
SCC Asynchronous HDLC Programming Example 25.17 SCC Asynchronous HDLC Programming Example The following example shows initialization for an SCC in asynchronous HDLC mode. 1. Initialize SDCR. 2. In NMSI mode, conﬁgure ports A and C to enable RXD, TXD, CTS, CD, and RTS. In other modes, conﬁgure the TSA and its pins.
Page 718 SCC Asynchronous HDLC Programming Example MPC850 Family User’s Manual...
Page 719 Chapter 26 SCC BISYNC Mode The byte-oriented BISYNC protocol was developed by IBM for use in networking products. There are three classes of BISYNC frames—transparent, nontransparent with header, and nontransparent without header, shown in Figure 26-1. The transparent frame type in BISYNC is not related to transparent mode, discussed in Chapter 28, “SCC Transparent Mode.”...
Page 720: Scc Bisync Channel Frame Transmission
Features transmission, an underrun must not occur between the DLE and its following character. This failure mode cannot occur with the MPC850. An SCC can be conﬁgured as a BISYNC controller to handle basic BISYNC protocol in normal and transparent modes. The controller can work with the time-slot assigner (TSA) or nonmultiplexed serial interface (NMSI).
Page 721: Scc Bisync Channel Frame Reception
SCC BISYNC Channel Frame Reception interrupt is issued according to TxBD[I]. TxBD[I] controls whether interrupts are generated after transmission of each buffer, a speciﬁc buffer, or each block. The controller then proceeds to the next BD. If no additional buffers have been sent to the controller for transmission, an in-frame underrun is detected and the controller starts sending syncs or idles.
Page 722: Scc Bisync Parameter Ram
• The controller can inspect data on a per-byte basis and interrupt the core each time a byte is received. • The controller can be programmed so software handles the ﬁrst two or three bytes. The controller directly handles subsequent data without interrupting the core. MPC850 Family User’s Manual...
Page 723: Scc Bisync Commands
SCC BISYNC Commands 26.5 SCC BISYNC Commands Transmit and receive commands are issued to the CP command register (CPCR). Transmit commands are described in Table 26-2. Table 26-2. Transmit Commands Command Description After hardware or software is reset and the channel is enabled in the GSMR, the channel is in transmit STOP enable mode and starts polling the ﬁrst BD every 64 transmit clocks.
Page 724: Scc Bisync Control Character Recognition
SCC Base 0x42 — CHARACTER1 0x44 — CHARACTER2 0x46 — CHARACTER3 0x48 — CHARACTER4 0x4A — CHARACTER5 0x4D — CHARACTER6 0x4E — CHARACTER7 0x50 — CHARACTER8 0x52 — MASK VALUE(RCCM) Figure 26-2. Control Character Table and RCCM MPC850 Family User’s Manual...
Page 725: Bisync Sync Register (Bsync)
BISYNC SYNC Register (BSYNC) Table 26-4 describes control character table and RCCM ﬁelds. Table 26-4. Control Character Table and RCCM Field Descriptions Offset Name Description 0x42–0x50 0 End of table. 0 This entry is valid. The lower eight bits are checked against the incoming character.
Page 726: Scc Bisync Dle Register (Bdle)
Table 26-6. BDLE Field Descriptions Bits Name Description Valid. If V = 1 and the receiver is not in hunt mode when a SYNC character is received, this character is discarded. 1–7 — All zeros 8–15 DLE character MPC850 Family User’s Manual...
Page 727: Sending And Receiving The Synchronization Sequence
Sending and Receiving the Synchronization Sequence 26.9 Sending and Receiving the Synchronization Sequence The BISYNC channel can be programmed to send and receive a synchronization pattern deﬁned in the DSR. GSMR_H[SYNL] deﬁnes pattern length, as shown in Table 26-7. The receiver synchronizes on this pattern.
Page 728: Bisync Mode Register (Psmr)
The PSMR is used as the BISYNC mode register, shown in Figure 26-5. PSMR[RBCS, RTR, RPM, TPM] can be modiﬁed on-the-ﬂy. Field RBCS RTR RVD DRT — Reset Addr 0xA28 (PSMR2), 0xA48 (PSMR3) Figure 26-5. Protocol-Specific Mode Register for BISYNC (PSMR) MPC850 Family User’s Manual...
Page 729 BISYNC Mode Register (PSMR) Table 26-10 describes PSMR ﬁelds. Table 26-10. PSMR Field Descriptions Bits Name Description 0–3 Minimum number of SYN1–SYN2 pairs (deﬁned in DSR) sent between or before messages.If NOS = 0000, one pair is sent. If NOS = 1111, 16 pairs are sent. The entire pair is always sent, regardless of how GSMR[SYNL) is set.
Page 730: Scc Bisync Receive Bd (Rxbd)
0 Not the ﬁrst buffer in the frame. 1 The ﬁrst buffer in the frame. First in frame. Set when this is the ﬁrst buffer in a frame. 0 Not the ﬁrst buffer in a frame. 1 First buffer in a frame MPC850 Family User’s Manual...
Page 731: Scc Bisync Transmit Bd (Txbd)
SCC BISYNC Transmit BD (TxBD) Table 26-11. SCC BISYNC RxBD Status and Control Field Descriptions (Continued) Bits Name Description Continuous mode. 0 Normal operation. 1 The CP does not clear E after this BD is closed; the buffer is overwritten when the CP accesses this BD next.
Page 732 Underrun. Set when the BISYNC controller encounters a transmitter underrun error while sending the associated data buffer. The CPM writes UN after it sends the associated buffer. CTS lost. The CP sets CT when CTS is lost during message transmission after it sends the data buffer. MPC850 Family User’s Manual...
Page 733: Bisync Event Register (Scce)/Bisync Mask Register (Sccm)
BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM) Data length and buffer pointer ﬁelds are described in Section 21.3, “SCC Buffer Descriptors (BDs).” Although it is never modiﬁed by the CP, data length should be greater than zero. The CPM writes these ﬁelds after it ﬁnishes sending the buffer. 26.14 BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM) The BISYNC controller uses the SCC event register (SCCE) to report events recognized by...
Page 734: Scc Status Registers (Sccs)
By setting the appropriate PSMR bit, the controller strips the leading DLE from DLE-character sequences. Thus, control characters are recognized only when they follow a DLE character. PSMR[RTR] should be cleared after a DLE-ETX is received. MPC850 Family User’s Manual...
Page 735: Scc Bisync Programming Example
SCC BISYNC Programming Example Alternatively, after an SOH is received, a should be issued to RESET BCS CALCULATION exclude SOH from BCS accumulation and reset the BCS. Notice that PSMR[RBCS] is not needed because the controller automatically excludes SYNCs and leading DLEs. After the type of block is recognized, SCCE[RCH] should be masked.
Page 736 Note that after 5 bytes are sent, the TxBD is closed. The buffer is closed after 16 bytes are received. Any received data beyond 16 bytes causes a busy (out-of-buffers) condition since only one RxBD is prepared. MPC850 Family User’s Manual...
Page 737: Scc Ethernet Mode
Chapter 27 SCC Ethernet Mode The Ethernet IEEE 802.3 protocol is a widely used LAN protocol based on the carrier sense multiple access/collision detect (CSMA/CD) approach. Because Ethernet and IEEE 802.3 protocols are similar and can coexist on the same LAN, both are referred to as Ethernet in this manual, unless otherwise noted.
Page 738: Ethernet On The Mpc850
EEST instead. The on-chip DPLL cannot be used for low-speed (1-Mbps) Ethernet either because it cannot properly detect start-of-frame or end-of-frame. Note that the CPM of the MPC850 requires a minimum system clock frequency of 24 MHz to support Ethernet.
Page 739: Features
Features 27.2 Features The following list summarizes the main features of the SCC in Ethernet mode: • Performs MAC layer functions of Ethernet and IEEE 802.3 • Performs framing functions — Preamble generation and stripping — Destination address checking — CRC generation and checking —...
Page 740: Parallel I/O Ports
MPC850. • Transmit clock (TCLK)—a CLKx signal routed through the bank of clocks on the MPC850. Note that RCLK and TCLK should not be connected to the same CLKx since the EEST provides separate transmit and receive clock signals. • Transmit data (TXD)—the MPC850 TXD signal.
Page 741 When sending, provide the destination address, source address, type/length ﬁeld, and the transmit data. To meet minimum frame requirements, the MPC850 pads frames with fewer than 46 bytes in the data ﬁeld and appends the FCS to the frame.
Page 742: Scc Ethernet Channel Frame Transmission
DMA transfer, and maximum frame length checking with almost no core intervention. When the core enables the Ethernet receiver, it enters hunt mode as soon as RENA is asserted while CLSN is negated. In hunt mode, as data is shifted into the receive MPC850 Family User’s Manual...
Page 743: Scc Ethernet Parameter Ram
SCC Ethernet Parameter RAM shift register one bit at a time, the register contents are compared to the contents of the SYN1 ﬁeld in the data synchronization register (DSR). This compare function becomes valid a certain number of clocks after the start of the frame (depending on PSMR[NIB]). If the two are not equal, the next bit is shifted in and the comparison is repeated.
Page 744 0x52 MAXD Hword Rx max DMA. 0x54 DMA_CNT Hword Rx DMA counter. A temporary down-counter used to track frame length. 0x56 MAX_B Hword Maximum BD byte count. MPC850 Family User’s Manual...
Page 745 SCC Ethernet Parameter RAM Table 27-1. SCC Ethernet Parameter RAM Memory Map (Continued) Offset Name Width Description 0x58 GADDR1 Hword Group address ﬁlter 1–4. Used in the hash table function of the group addressing mode. Write zeros to these values after reset and before the Ethernet channel is GADDR2 0x5A enabled to disable all group hash address recognition functions.
Page 746: Programming The Ethernet Controller
After receiving the command, the buffer is closed and the CRC calculation is reset. The next RxBD is used to receive more frames. Should not be used with the Ethernet controller. CLOSE RXBD MPC850 Family User’s Manual...
Page 747: Scc Ethernet Address Recognition
SCC Ethernet Address Recognition Table 27-3. Receive Commands (Continued) Command Description Initializes receive parameters in this serial channel parameter RAM to their reset state. Issue it only INIT RX when the receiver is disabled. resets receive and transmit parameters. PARAMETERS INIT TX RX PARAMETERS Used to set one of the 64 bits of the four individual/group address hash ﬁlter registers.
Page 748: Hash Table Algorithm
48-bit address into one of 64 bins, each represented by a bit stored in GADDRx or IADDRx. When a command is executed, the Ethernet controller SET GROUP ADDRESS maps the selected 48-bit address into one of the 64 bits by passing the 48-bit address MPC850 Family User’s Manual...
Page 749: Interpacket Gap Time
Interpacket Gap Time through the on-chip 32-bit CRC generator and selecting 6 bits of the CRC-encoded result to generate a number between 1 and 64. Bits 31–30 of the CRC result select one of the GADDRs or IADDRs; bits 29–26 of the CRC result indicate the bit in that register. When the Ethernet controller receives a frame, the same process is used.
Page 750: Full-Duplex Ethernet Support
This heartbeat condition does not imply a collision error, but that the transceiver seems to be functioning properly. If SCCE[HBC] = 1 and the MPC850 does not detect a heartbeat condition after sending a frame, a heartbeat error occurs; the channel closes the buffer, sets the HB bit in the TxBD, and generates the TXE interrupt if it is enabled.
Page 751: Ethernet Mode Register (Psmr)
0 Normal operation. 1 The channel forces a collision when each frame is sent. To test collision logic conﬁgure the MPC850 in loopback operation. In the end, the retry limit for each transmit frame is exceeded. Receive short frames. 0 Discard short frames that are not as long as MINFLR.
Page 752: Scc Ethernet Receive Buffer Descriptor
The Ethernet controller uses the RxBD to report on the received data for each buffer. Offset + 0 — — — Offset + 2 Data Length Rx Data Buffer Pointer Offset + 4 Offset + 6 Figure 27-6. SCC Ethernet RxBD MPC850 Family User’s Manual...
Page 753 SCC Ethernet Receive Buffer Descriptor Table 27-7 describes RxBD status and control ﬁelds. Table 27-7. SCC Ethernet RxBD Status and Control Field Descriptions Bits Name Description Empty. 0 The buffer is full or stopped receiving data because an error occurred. The core can read or write any ﬁelds of this RxBD.
Page 754: Scc Ethernet Transmit Buffer Descriptor
Data is sent to the Ethernet controller for transmission on an SCC channel by arranging it in buffers referenced by the channel TxBD table. The Ethernet controller uses TxBDs to conﬁrm transmission or indicate errors so the core knows buffers have been serviced. MPC850 Family User’s Manual...
Page 755 SCC Ethernet Transmit Buffer Descriptor Offset + 0 Data Length Offset + 2 Tx Data Buffer Pointer Offset + 4 Offset + 6 Figure 27-8. SCC Ethernet TxBD Table 27-8 describes TxBD status and control ﬁelds. Table 27-8. SCC Ethernet TxBD Status and Control Field Descriptions Bits Name Description...
Page 756: Scc Ethernet Event Register (Scce)/Mask Register (Sccm)
Busy condition. Set when a frame is received and discarded due to a lack of buffers. Tx buffer. Set when a buffer has been sent on the Ethernet channel. Rx buffer. Set when a buffer that was not a complete frame was received on the Ethernet channel. MPC850 Family User’s Manual...
Page 757: Scc Ethernet Programming Example
SCC Ethernet Programming Example Figure 27-10 shows an example of interrupts that can be generated in Ethernet protocol. Frame Received in Ethernet Stored in Rx Buffer Time P SFD DA SA Line Idle Line Idle RENA Ethernet SCCE Events NOTES 1.
Page 758 24. Clear TADDR_H, TADDR_M, and TADDR_L for clarity. 25. Initialize the RxBD and assume the Rx data buffer is at 0x0000_1000 in main memory. Write 0xB000 to RxBD[Status and Control], 0x0000 to RxBD[Data Length] (optional), and 0x0000_1000 to RxBD[Buffer Pointer]. MPC850 Family User’s Manual...
Page 759 Ethernet mode. TCI is set to allow more setup time for the EEST to receive the MPC850 transmit data. TPL and TPP are set for Ethernet requirements. The DPLL is not used with Ethernet. Note that the ENT and ENR are not enabled yet.
Page 760 SCC Ethernet Programming Example MPC850 Family User’s Manual...
Page 761: Features
Chapter 28 SCC Transparent Mode Transparent mode (also called totally transparent or promiscuous mode) provides a clear channel on which the SCC can send or receive serial data without bit-level manipulation. Software implements protocols run over transparent mode. An SCC in transparent mode functions as a high-speed serial-to-parallel and parallel-to-serial converter.
Page 762: Scc Transparent Channel Frame Transmission Process
After a buffer is full, the SCC clears RxBD[E] and generates a maskable interrupt if RxBD[I] is set. It moves to the next RxBD in the table and begins moving data to its buffer. If the next buffer is not available, SCCE[BSY] signiﬁes a busy signal that can generate a MPC850 Family User’s Manual...
Page 763: Achieving Synchronization In Transparent Mode
Achieving Synchronization in Transparent Mode maskable interrupt. The receiver reverts to hunt mode when an ENTER HUNT MODE command or an error is received. If GSMR_H[REVD] is set, the bit order of each byte is reversed before it is written to memory. Setting GSMR_H[RFW] reduces receiver latency by making the receive FIFO smaller, which may cause receiver overruns at higher transmission speeds.
Page 764: External Synchronization Signals
Notes: • 1. Each MPC850 generates its own transmit clocks. If the transmit and receive clocks are the same, one MPC850 can generate transmit and receive clocks for the other MPC850. For example, CLKx on MPC850(B) could be used to clock the transmitter and receiver.
Page 765: Transparent Mode Without Explicit Synchronization
MPC850(A) and MPC850(B) exchange transparent frames and synchronize each other using RTS and CD. However, CTS is not required because transmission begins at any time. Thus, RTS is connected directly to the other MPC850 CD pin. GSMR_H[RSYN] is not used and transmission and reception from each MPC850 are independent.
Page 766: Inherent Synchronization
Thus, the user can choose an HDLC transmitter with a transparent receiver or a transparent transmitter with an HDLC receiver. 28.7 SCC Transparent Commands The following transmit and receive commands are issued to the CP command register. MPC850 Family User’s Manual...
Page 767: Handling Errors In The Transparent Controller
Handling Errors in the Transparent Controller Table 28-3 describes transmit commands. Table 28-3. Transmit Commands Command Description After hardware or software is reset and the channel is enabled in the GSMR, the channel is in transmit STOP enable mode and starts polling the ﬁrst BD every 64 clocks (or immediately if TODR[TOD] = 1). TRANSMIT STOP disables frame transmission on the transmit channel.
Page 768: Transparent Mode And The Psmr
• An error is detected. • A full receive buffer is detected. • An command is Issued. ENTER HUNT MODE • A command is issued. CLOSE RXBD MPC850 Family User’s Manual...
Page 769 SCC Transparent Receive Buffer Descriptor (RxBD) Offset + 0 — — — — Offset + 2 Data Length Rx Buffer Pointer Offset + 4 Offset + 6 Figure 28-2. SCC Transparent Receive Buffer Descriptor (RxBD) Table 28-7 describes RxBD status and control ﬁelds. Table 28-7.
Page 770: Scc Transparent Transmit Buffer Descriptor (Txbd)
1 Last BD in the table. After this buffer is used, the CPM receives incoming data into the ﬁrst BD that TBASE points to. The number of TxBDs in this table is determined only by TxBD[W] and overall space constraints of the dual-port RAM. MPC850 Family User’s Manual...
Page 771: Scc Transparent Event Register (Scce)/Mask Register (Sccm)
SCC Transparent Event Register (SCCE)/Mask Register (SCCM) Table 28-8. SCC Transparent Tx BD Status and Control Field Descriptions (Continued) Name Description Interrupt. Note that clearing this bit does not disable SCCE[TXE]. 0 No interrupt is generated after this buffer is serviced. 1 When the CPM services this buffer, SCCE[TXB] or SCCE[TXE] is set.
Page 772: Scc Status Register In Transparent Mode (Sccs)
28.13 SCC Status Register in Transparent Mode (SCCS) The SCC status register (SCCS) allows monitoring of real-time status conditions on the RXD line. The real-time status of CTS and CD are part of the port C parallel I/O. MPC850 Family User’s Manual...
Page 773: Scc2 Transparent Programming Example
The following initialization sequence enables the transmitter and receiver, which operate independently of each other. The sequence implements the connection shown for MPC850(B) in Figure 28-1. The transparent controller is conﬁgured with RTS2 and CD2 active, and CTS2 is conﬁgured to be grounded internally in port C. CLK3 externally provides the transmit and receive clocks.
Page 774 Note that after 5 bytes are sent, the Tx buffer is closed and after 16 bytes are received the Rx buffer is closed. Any data received after 16 bytes causes a busy (out-of-buffers) condition since only one RxBD is prepared. MPC850 Family User’s Manual...
Page 775 • Low speed—2.4 Kbps to 115.2 Kbps • Middle speed—0.576 Mbps or 1.152 Mbps • High speed—4 Mbps Figure 29-1 shows how to implement a serial infrared link using the SCC2’s IrDA encoder/decoder module and an external IrDA transducer module. MPC850 Encoder/Decoder IR Transducer Module Module IR Transmit Output Driver &...
Page 776: Low-Speed Irda Protocol
The waveform is shown in Figure 29-4(b). For 0.576 and 1.152 Mbps, the minimum and maximum pulse duration are the nominal of the bit duration (plus or minus the protocol deﬁned tolerance). MPC850 Family User’s Manual...
Page 777: High-Speed Irda Protocol
High-Speed IrDA Protocol DATA BITS 1/4 BIT TIME Figure 29-4. Middle-Speed IrDA Data Format 29.3 High-Speed IrDA Protocol The high-speed IrDA protocol is derived from the transparent SCC protocol standard. 29.3.1 4PPM Data Encoding Deﬁnition Pulse position modulation (PPM) encoding is achieved by deﬁning a data symbol duration (Dt) and subsequently subdividing it into a set of equal time slices, or chips.
Page 778: Data Link Layer
The receiver continues to receive and interpret data until the stop ﬂag (STO) is recognized. STO indicates the end of frame and consists of exactly one transmission of the following stream of symbols. MPC850 Family User’s Manual...
Page 779: Serial Infrared Interaction Pulses
High-Speed IrDA Protocol 0000 1100 0000 1100 0000 1100 0000 1100 Figure 29-9. Stop Flag Symbol Format The physical layer deﬁnes the electrical parameters of the signals between the encoder/decoder module and the IR transducer module. All frame envelope patterns—PA, STA, and STO—are sent as is.
Page 780: Irda Registers
10 20x bit rate clock. 11 Reserved. Full duplex. This bit should be set in loopback mode. 0 Data reception is disabled during a transmission process. 1 Transmission and reception of data in parallel are enabled. MPC850 Family User’s Manual...
Page 781: Infrared Serial Interaction Control Register (Irsip)
IrDA Registers Table 29-2. IRMODE Field Descriptions (Continued) Name Description LOOP Loop mode. Enables local loopback operation. 0 Normal operation. 1 The IrDA is in loopback mode. The transmitter output is internally connected to the receiver input. The receiver and transmitter operate normally except that the received data is ignored. —...
Page 782: Low-Speed Irda Programming
20. Program the GSMR_L register to asynchronous HDLC mode, but do not turn on the transmitter or receiver. 21. Write 0x0001 to the IRMODE register to enable the IR. 22. Set the PSMR register appropriately. 23. Turn on the transmitter and receiver by setting GSMR_L[ENT, ENR]. MPC850 Family User’s Manual...
Page 783: Middle-Speed Irda Programming
Middle-Speed IrDA Programming 29.6 Middle-Speed IrDA Programming Middle-speed infra-red programming is very similar to SCC synchronous HDLC programming. The parameter RAM programming and the RxBDs and TXBDs are the same as in the SCC synchronous HDLC. All SCC2 synchronous registers and the infrared registers must be initialized.
Page 784: High-Speed Irda Programming Example
The following is an initialization sequence for a high-speed infrared channel. The transmitter and receiver are both enabled. Both transmit and receive clocks are provided externally to MPC850 using CLK3. 1. Conﬁgure the port A pins to enable the TXD2 and RXD2 pins. Set PAPAR[12,13] and clear PADIR[12,13].
Page 785 High-Speed IrDA Programming Example 6. Write RBASE and TBASE in the SCC2 parameter RAM to point to the RxBD and TxBD in the dual-port RAM. Assuming one RxBD followed by one TxBD at the beginning of dual-port RAM, write RBASE with 0x2000 and TBASE with 0x2008. 7.
Page 786 High-Speed IrDA Programming Example MPC850 Family User’s Manual...
Page 787 Chapter 30 Serial Management Controllers (SMCs) The two serial management controllers (SMCs) are full-duplex ports that can be conﬁgured independently to support one of three protocols—UART, transparent, or general-circuit interface (GCI). Simple UART operation is used to provide a debug/monitor port in an application, which allows the SCCs to be free for other purposes.
Page 788: Smc Features
(NMSI) line. The transparent mode can also be used for a fast connection between MPC850s. However, if SMC2 is connected to the NMSI, the TDM channel is unavailable. • Each SMC channel fully supports the C/I and monitor channels of the GCI (IOM-2) in ISDN applications MPC850 Family User’s Manual...
Page 789: Smc Mode Registers (Smcmrn)
Common SMC Settings and Conﬁgurations • Two SMCs support the two sets of C/I and monitor channels in the SCIT channels 0 and 1 • Full-duplex operation • Local loopback and echo capability for testing 30.2 Common SMC Settings and Conﬁgurations The following sections describe settings and conﬁgurations that are common to the serial management controllers.
Page 790 1 Reverse the character bit order. The msb is sent ﬁrst. SCIT channel number. (GCI) 0 SCIT channel 0 1 SCIT channel 1. Required for Siemens ARCOFI and SGS S/T chips. 8–9 — Reserved, should be cleared MPC850 Family User’s Manual...
Page 791: Smc Buffer Descriptors (Bds)
Common SMC Settings and Conﬁgurations Table 30-1. SMCMR Field Descriptions (Continued) Bits Name Description 10–11 SM SMC mode. 00 GCI or SCIT support. 01 Reserved. 10 UART (must be selected for SMC UART operation). 11 Totally transparent operation. 12–13 DM Diagnostic mode.
Page 792: Smc Parameter Ram
0x06 MRBLR Hword Maximum receive buffer length. The most bytes the MPC850 writes to a Rx buffer before moving to the next buffer. It can write fewer bytes than MRBLR if a condition like an error or end-of-frame occurs, but it cannot exceed MRBLR. Rx buffers should not be smaller than MRBLR.
Page 793: Smc Function Code Registers (Rfcr/Tfcr)
Common SMC Settings and Conﬁgurations Table 30-2. SMC UART and Transparent Parameter RAM Memory Map (Continued) Offset Name Width Description 0x14 — Word Rx temp. Can be used only by the CP. 0x18 TSTATE Word Tx internal state. Can be used only by the CP. 0x1C —...
Page 794: Disabling Smcs On-The-Fly
3. RESTART TRANSMIT INIT TX PARAMETERS 5. Set SMCMR[TEN]. Transmission now begins using the TxBD that the TBPTR value points to as soon as the R bit is set in that TxBD. MPC850 Family User’s Manual...
Page 795: Smc Transmitter Shortcut Sequence
Common SMC Settings and Conﬁgurations 30.2.4.2 SMC Transmitter Shortcut Sequence This shorter sequence reinitializes transmit parameters to the state they had after reset. 1. Clear SMCMR[TEN]. 2. Make any changes, then issue an command. INIT TX PARAMETERS 3. Set SMCMR[TEN]. 30.2.4.3 SMC Receiver Full Sequence Follow these steps to fully enable or disable the receiver: 1.
Page 796: Smc In Uart Mode
The following list summarizes the main features of the SMC in UART mode: • Flexible message-oriented data structure • Programmable data length (5–14 bits) • Programmable 1 or 2 stop bits • Even/odd/no parity generation and checking • Frame error, break, and IDLE detection MPC850 Family User’s Manual...
Page 797: Smc Uart-Specific Parameter Ram
SMC in UART Mode • Transmit preamble and break sequences • Received break character length indication • Continuous receive and transmit modes 30.3.2 SMC UART-Speciﬁc Parameter RAM For UART mode, the protocol-speciﬁc area of the SMC parameter RAM is mapped as in Table 30-4.
Page 798: Smc Uart Channel Reception Process
In a message-oriented environment, an idle sequence is used as the message delimiter. The transmitter can generate an idle sequence before starting a new message and the receiver can close a buffer when an idle sequence is found. MPC850 Family User’s Manual...
Page 799: Smc Uart Commands
SMC in UART Mode 30.3.6 SMC UART Commands Table 30-5 describes transmit commands issued to the CPCR. Table 30-5. Transmit Commands Command Description Disables transmission of characters on the transmit channel. If the SMC UART controller receives this STOP command while sending a message, it stops sending. The SMC UART controller ﬁnishes sending any TRANSMIT data that has already been sent to its FIFO and shift register and then stops sending data.
Page 800: Handling Errors In The Smc Uart Controller
• A programmable number of consecutive idle characters are received Offset + 0 — — — — — Offset + 2 Data Length Offset + 4 Rx Buffer Pointer Offset + 6 Figure 30-6. SMC UART Receive BD (RxBD) MPC850 Family User’s Manual...
Page 801 SMC in UART Mode Table 30-8 describes SMC UART RxBD status and control ﬁelds. Table 30-8. SMC UART RxBD Status and Control Field Descriptions Name Description Empty. 0 The buffer is full or data reception stopped due to an error. The core can read or write any ﬁelds of this RxBD.
Page 802 Idle Count Expires Still in Progress (MAX_IDL) with this Buffer 10 Characters 5 Characters Long Idle Period Characters Received by UART Fourth Character Present Time has Framing Error! Time Figure 30-7. SMC UART Receiving using RxBDs MPC850 Family User’s Manual...
Page 803: Smc Uart Transmit Bd (Txbd)
SMC in UART Mode 30.3.11 SMC UART Transmit BD (TxBD) Data is sent to the CPM for transmission on an SMC channel by arranging it in buffers referenced by descriptors in the channel’s TxBD table. Using the BDs, the CP confirms transmission or indicates error conditions so that the processor knows the buffers have been serviced.
Page 804: Smc Uart Event Register (Smce)/Mask Register (Smcm)
Rx buffer. Set when a buffer is received and its associated RxBD is closed. Set no sooner than the middle of the last stop bit of the last character that is written to the receive buffer. MPC850 Family User’s Manual...
Page 805: Smc Uart Controller Programming Example
SMC in UART Mode Figure 30-10 shows an example of the timing of various events in the SMCE. Characters Received by SMC UART 10 Characters Time Line Idle Line Idle Break SMC UART SMCE BRKE Events NOTES: 1. The first RX event assumes receive buffers are 6 bytes each. 2.
Page 806: Smc In Transparent Mode
However, the SMC in transparent mode provides a data character length option of 4 to 16 bits, whereas the SCCs provide 8 or 32 bits, depending on GSMR[RFW]. The SMC in transparent mode is also referred to as the SMC transparent controller. MPC850 Family User’s Manual...
Page 807: Smc Transparent Mode Features
SMC in Transparent Mode 30.4.1 SMC Transparent Mode Features The following list summarizes the features of the SMC in transparent mode: • Flexible buffers • Can connect to a TDM bus using the TSA in the SI • Can transmit and receive transparently on its own set of pins using a sync pin to synchronize the beginning of transmission and reception to an external event •...
Page 808: Smc Transparent Channel Reception Process
Glitches on SMSYN can cause erratic behavior of the SMC. The transmitter and receiver never lose synchronization again, regardless of the state of SMSYN, until the TEN bit is cleared or an command is issued. ENTER HUNT MODE MPC850 Family User’s Manual...
Page 809: Using Tsa For Synchronization
SMC in Transparent Mode SMCLK SMSYN SMTXD 1s are sent Five 1s are sent SMC1 Transmit Data TEN set SMSYN Tx FIFO Five 1s First bit of Transmission here detected loaded assume first 5-bit could begin low here approximately character transmit here if Tx FIFO here...
Page 810 • If a buffer is made ready after its SMC is enabled, the ﬁrst byte can appear in any time slot associated with this channel. • If a buffer is closed with BD[L] set, then the next buffer can appear in any time slot associated with this channel. MPC850 Family User’s Manual...
Page 811: Smc Transparent Commands
SMC in Transparent Mode If the SMC runs out of transmit buffers and a new buffer is provided later, idles are sent in the gap between buffers. Data transmission from the later buffer begins at the start of an SMC time slot, but not necessarily the ﬁrst time slot after the frame sync. So, to maintain a certain bit alignment beginning with the ﬁrst time slot, make sure that at least one TxBD is always ready and that underruns do not occur.
Page 812: Handling Errors In The Smc Transparent Controller
1 The buffer is empty or is receiving data. The CP owns this RxBD and its buffer. Once E is set, the core should not write any ﬁelds of this RxBD. — Reserved, should be cleared. MPC850 Family User’s Manual...
Page 813: Smc Transparent Transmit Bd (Txbd)
SMC in Transparent Mode Table 30-14. SMC Transparent RxBD Field Descriptions (Continued) Bits Name Description Wrap (last BD in RxBD table). 0 Not the last BD in the table. 1 Last BD in the table. After this buffer is used, the CP receives incoming data into the ﬁrst BD that RBASE points to.
Page 814: External Memory
8 bits, in which case the transmit buffer pointer must be even. For instance, the pointer to 8-bit transparent characters can be even or odd, but the pointer to 9-bit transparent characters must be even. The buffer can reside in internal or external memory. MPC850 Family User’s Manual...
Page 815: Smc Transparent Event Register (Smce)/Mask Register (Smcm)
SMC in Transparent Mode 30.4.11 SMC Transparent Event Register (SMCE)/Mask Register (SMCM) The SMC event register (SMCE) generates interrupts and reports events recognized by the SMC channel. When an event is recognized, the SMC sets the corresponding SMCE bit. Interrupts are masked in the SMCM, which has the same format as the SMCE. SMCE bits are cleared by writing ones;...
Page 816: Smc Transparent Tsa Programming Example
TSA. It is assumed that the TSA and the TDM pins have been set up to route time-slot data to the SMC transmitter and receiver. Chapter 20, “Serial Interface,” has examples for conﬁguring the TSA which provides transmit and receive clocks and synchronization signals internally. MPC850 Family User’s Manual...
Page 817: Smc In Gci Mode
SMC in GCI Mode 1. Write RBASE and TBASE in the SMC parameter RAM to point to the RxBD and TxBD in the dual-port RAM. Assuming one RxBD at the beginning of the dual-port RAM followed by one TxBD, write RBASE with 0x0000 and TBASE with 0x0008. 2.
Page 818: Smc Gci Parameter Ram
The SMC receives data and handles the A and E control bits according to the GCI monitor channel protocol. When the CP stores a received data byte in the SMC RxBD, a maskable interrupt is generated. A command causes the MPC850 to send TRANSMIT ABORT REQUEST an abort request on the E bit.
Page 819: Handling The Gci C/I Channel
It is usually issued because the device is not responding or A bit errors are detected. The MPC850 sends an abort request on the E bit at the time this command is issued. 30.5.5 SMC GCI Monitor Channel RxBD The GCI monitor channel RxBD, shown in Figure 30-16, is used by the CP to report on the monitor channel receive byte.
Page 820: Smc Gci Monitor Channel Txbd
Abort request. Set by the SMC when an abort request is received on the A bit. The transmitter sends the EOM on the E bit after receiving an abort request. 3–7 — Reserved, should be cleared. Data 8–15 Data ﬁeld. Contains the data to be sent by the SMC on the monitor channel. MPC850 Family User’s Manual...
Page 821: Smc Gci C/I Channel Rxbd
SMC in GCI Mode 30.5.7 SMC GCI C/I Channel RxBD The GCI C/I channel RxBD, shown in Figure 30-18, is used by the CP to report on the C/I channel receive byte. The RxBD itself receives the C/I data. Offset + 0 —...
Page 822: Smc Gci Event Register (Smce)/Mask Register (Smcm)
C/I channel buffer received. Set when the C/I receive buffer becomes full. MTXB Monitor channel buffer transmitted. Set when the monitor transmit buffer becomes empty. MRXB Monitor channel buffer received. Set when the monitor receive buffer becomes full. MPC850 Family User’s Manual...
Page 823 Chapter 31 Serial Peripheral Interface (SPI) The serial peripheral interface (SPI) allows the MPC850 to exchange data between other MPC850 chips, the MC68360, the MC68302, the M68HC11 and M68HC05 microcontroller families, and peripheral devices such as EEPROMs, real-time clocks, A/D converters, and ISDN devices.
Page 824: Spi Clocking And Signal Functions
SPI signal is driven by the MPC850 or an external SPI device. The SPI master-in slave-out SPIMISO signal acts as an input for master devices and as an output for slave devices.
Page 825: The Spi As A Master Device
In master mode, the SPI sends a message to the slave peripheral, which sends back a simultaneous reply. A single master MPC850 with multiple slaves can use general-purpose parallel I/O signals to selectively enable slaves, as shown in Figure 31-2. To eliminate the multimaster error in a single-master environment, the master’s SPISEL input can be forced...
Page 826 SPIMOSI between buffers. If the current TxBD[L] is set, sending stops after the current buffer is sent. In addition, the RxBD is closed after transmission stops, even if the Rx buffer is not full; therefore, Rx buffers need not be the same length as Tx buffers. MPC850 Family User’s Manual...
Page 827: The Spi As A Slave Device
Conﬁguring the SPI Controller 31.3.2 The SPI as a Slave Device In slave mode, the SPI receives messages from an SPI master and sends a simultaneous reply. The slave’s SPISEL must be asserted before Rx clocks are recognized; once SPISEL is asserted, SPICLK becomes an input from the master to the slave.
Page 828 • It is the responsibility of software to arbitrate for the SPI bus (with token passing, for example) • SELOUTx signals are implemented in software with general-purpose I/O signals Figure 31-3. Multimaster Configuration MPC850 Family User’s Manual...
Page 829: Spi Registers
SPI Registers 31.4 SPI Registers The following sections describe the registers used in conﬁguring and operating the SPI. 31.4.1 SPI Mode Register (SPMODE) The SPI mode register (SPMODE), shown in Figure 31-4, controls both the SPI operation mode and clock source. Field —...
Page 830: Spi Transfers With Different Clocking Modes
(SPMODE[CP] = 1). SPICLK (CI = 0) SPICLK (CI = 1) SPIMOSI (From Master) SPIMISO (From Slave) SPISEL NOTE: Q = Undefined Signal. Figure 31-6. SPI Transfer Format with SPMODE[CP] = 1 MPC850 Family User’s Manual...
Page 831: Spi Examples With Different Spmode[Len] Values
SPI Registers 31.4.1.2 SPI Examples with Different SPMODE[LEN] Values The examples below show how SPMODE[LEN] is used to determine character length. To help map the process, the conventions shown in Table 31-2 are used in the examples. Table 31-2. Example Conventions Convention Description –...
Page 832: Spi Event/Mask Registers (Spie/Spim)
Rx buffer. Set after the last character is written to the Rx buffer and the BD is closed. 31.4.3 SPI Command Register (SPCOM) The SPI command register (SPCOM), shown in Figure 31-8, is used to start SPI operation. Field — Reset Addr 0xAAD Figure 31-8. SPI Command Register (SPCOM) MPC850 Family User’s Manual...
Page 833: Spi Parameter Ram
Maximum receive buffer length. The SPI has one MRBLR entry to deﬁne the maximum number of bytes the MPC850 writes to a Rx buffer before moving to the next buffer. The MPC850 can write fewer bytes than MRBLR if an error or end-of-frame occurs, but never exceeds the MRBLR value.
Page 834: Receive/Transmit Function Code Registers (Rfcr/Tfcr)
1x Big-endian or true little-endian. AT[1–3] Address type 1–3. Contains the user-deﬁned function code value used during the SDMA channel 5–7 memory access. AT0 is always driven high to identify this channel access as a DMA-type access. MPC850 Family User’s Manual...
Page 835: Spi Commands
SPI Commands 31.6 SPI Commands Table 31-7 lists transmit/receive commands sent to the CPM command register (CPCR). Table 31-7. SPI Commands Command Description Initializes all transmit parameters in the parameter RAM to their reset state and should be issued only INIT TX when the transmitter is disabled.
Page 836: Spi Receive Bd (Rxbd)
SPI is enabled. The format of an RxBD is shown in Figure 31-11. Offset + 0 — — — Offset + 2 Data Length Offset + 4 Rx Buffer Pointer Offset + 6 Figure 31-11. SPI Receive BD (RxBD) MPC850 Family User’s Manual...
Page 837: Spi Transmit Bd (Txbd)
The SPI Buffer Descriptor (BD) Table Table 31-8 describes the RxBD status and control ﬁelds. Table 31-8. SPI RxBD Status and Control Field Descriptions Bits Name Description Empty. 0 The buffer is full or stopped receiving because of an error. The core can examine or write to any ﬁelds of this RxBD, but the CPM does not use this BD while E = 0.
Page 838: Spi Master Programming Example
3. Write RBASE and TBASE in the SPI parameter RAM to point to the RxBD and TxBD tables in the dual-port RAM. Assuming one RxBD followed by one TxBD at the beginning of the dual-port RAM, write RBASE with 0x0000 and TBASE with 0x0008. MPC850 Family User’s Manual...
Page 839: Spi Slave Programming Example
SPI Slave Programming Example 4. Execute the command by writing 0x0051 to CPCR. INIT RX AND TX PARAMETERS 5. Write 0x0001 to the SDCR to initialize the SDMA conﬁguration register (SDCR). 6. Write RFCR and TFCR with 0x10 for normal operation. 7.
Page 840: Handling Interrupts In The Spi
2. Process the TxBD to reuse it and the RxBD to extract the data from it. To transmit another buffer, simply set TxBD[R], RxBD[E], and SPCOM[STR]. 3. Clear the interrupt by writing a one to CISR[SPI]. 4. Execute an rfi instruction. MPC850 Family User’s Manual...
Page 841: Overview
32.1 Overview The universal serial bus (USB) is an industry-standard extension to the PC architecture. The USB controller on the MPC850 supports data exchange between a PC host and a wide range of simultaneously accessible peripherals. Attached peripherals share USB bandwidth through a host-scheduled, token-based protocol.
Page 842: Features
• Flexible data buffers with multiple buffers per frame • Automatic retransmission upon transmit error The following list summarizes the USB host controller features: • Supports control, bulk, interrupt, and isochronous data transfers • CRC16 generation and checking • NRZI encoding/decoding with bit stufﬁng MPC850 Family User’s Manual...
Page 843: Host Controller Limitations
• Scheduling the various transfers within and between frames Because the MPC850 USB host controller does not integrate the root hub, an external hub is required when more than one device is connected to the host. An external hub is also required for low-speed operation.
Page 844 The source for USBCLK is selected in SICR[R1CS]; see Section 20.2.4.3, “SI Clock Route Register (SICR).” The MPC850 can run at different frequencies, but the USB reference clock must be four times the USB bit rate. Thus, USBCLK must be 48 MHz for a 12-Mbps full-speed transfer or 6 MHz for a 1.5-Mbps...
Page 845: Sending And Receiving
Sending and Receiving 32.5 Sending and Receiving After reset, the USB slave controller is addressable at the USB default address (0x00). The external host assigns a unique address (other than 0x00) to the controller during enumeration. Software should program the USB slave address register (USADR) with the assigned address.
Page 846 If the host fails to acknowledge the packet, the timeout status bit TxBD[TO] is set. Software must set the proper DATA0/DATA1 PID in the transmitted packet. USB In Token Reception USEPn[THS] FIFO Loaded Handshake Sent to Host 00 (Normal) 01 (Ignore) — None 10 (NAK) — 11 (STALL) — STALL MPC850 Family User’s Manual...
Page 847: Usb Parameter Ram
USB Parameter RAM Table 32-2. USB Tokens (Continued) Token Description SETUP The format of setup transactions is similar to OUT but uses a SETUP rather than an OUT PID. A SETUP token is recognized only by a control endpoint. When a SETUP token is received, setup reception begins. The USB controller fetches the next BD associated with the endpoint;...
Page 848 USB receive buffer before moving to the next buffer. MRBLR must be divisible by 4. The MPC850 can write fewer data bytes to the buffer than the MRBLR value if a condition such as an error or end-of-packet occurs, but it never exceeds MRBLR.
Page 849 USB Parameter RAM Table 32-4. Endpoint Parameter Block (Continued) Offset Name Width Description 0X0C TSTATE 32 bits Transmit internal state. Reserved for CP use only. Should be cleared before enabling the USB controller. 0x10 TPTR 32 bits Transmit internal data pointer. Updated by the SDMA channels to show the next address in the buffer to be accessed.
Page 850: Usb Registers
Reserved, should be cleared. TEST Test mode. 0 Normal operation. 1 Local loopback mode. In this mode, if the HOST bit is set, endpoint 0 operates as host and endpoints 1–3 can be used as function endpoints. MPC850 Family User’s Manual...
Page 851: Usb Slave Address Register (Usadr)
USB Registers Table 32-7. USMOD Field Descriptions (Continued) Bits Name Description HOST Host mode. 0 The USB controller implements a USB function. 1 The USB controller implements a USB host. Endpoint 0 operates as host. Endpoints 1–3 are not used, unless the TEST bit is set. Enable USB.
Page 852: Usb Command Register (Uscom)
11 Force STALL handshake. Not allowed for control endpoint. 32.7.4 USB Command Register (USCOM) The USB command (USCOM) register, shown in Figure 32-10, is used to start USB transmit operation. Field FLUSH — Reset 0000_0000 Addr 0xA02 Figure 32-10. USB Command Register (USCOM) MPC850 Family User’s Manual...
Page 853: Usb Event Register (Usber)/Mask Register (Usbmr)
USB Registers Table 32-10 describes USCOM ﬁelds. Table 32-10. USCOM Field Descriptions Bits Name Description Start FIFO ﬁll. Setting STR causes the USB controller to start ﬁlling the corresponding endpoint transmit FIFO with data. Transmission begins when the IN token for this endpoint is received. STR is always read as a zero.
Page 854: Usb Status Register (Usbs)
Table 32-12. USBS Field Descriptions Bits Name Description 0–6 — Reserved and should be cleared. IDLE Idle status. Set when an idle condition is detected on the USB lines. Cleared when the bus is not idle. MPC850 Family User’s Manual...
Page 855: Usb Buffer Descriptor Tables
USB Buffer Descriptor Tables 32.8 USB Buffer Descriptor Tables Data associated with the USB controller is stored in buffers, which are referenced by BDs organized in BD tables in the dual-port RAM. These tables have the same basic conﬁguration as those used by the SCCs and SMCs. Each endpoint has a separate transmit BD table and a separate receive BD table.
Page 856 RxBD Table Rx Buffer Descriptors EP0 RxBD Table Pointer EP0 TxBD Table Pointer Status and Control Data Length Rx Data Buffer EP3 RxBD Buffer Pointer Table Pointer EP3 TxBD Table Pointer Figure 32-13. USB Memory Structure MPC850 Family User’s Manual...
Page 857: Usb Receive Buffer Descriptor (Rxbd)
USB Buffer Descriptor Tables 32.8.1 USB Receive Buffer Descriptor (RxBD) The CP reports information about each buffer of received data using RxBDs. The CP closes the current buffer, generates a maskable interrupt, and starts receiving data in the next buffer when the current buffer is full.
Page 858: Usb Transmit Buffer Descriptor (Txbd)
Figure 32-15. USB Transmit Buffer Descriptor (TxBD) The ﬁrst half word of a TxBD contains status and control bits. The user prepares these bits before starting transmission; the CP updates the status bits after the buffer has been closed. MPC850 Family User’s Manual...
Page 859 USB Buffer Descriptor Tables (Note that the user is responsible for clearing status bits.) Table 32-14. describes TxBD status and control ﬁelds. Table 32-14. TxBD Status and Control Field Descriptions Bits Name Description Ready. Prepare this bit before transmitting data. 0 The buffer is not ready for transmission.
Page 860: Usb Cp Commands
(SCCs, USB, SMCs, SPI, and I as well as the CPM and RISC timer table. RST does not, however, affect the serial interface or parallel I/O registers. 0 No reset issued. 1 Reset issued. — Reserved. Should be cleared. MPC850 Family User’s Manual...
Page 861: Usb Controller Errors
USB Controller Errors Table 32-15. USB Command Format Field Descriptions (Continued) Bits Name Description 2–3 USBCMD Contains the USB command. 01 The command disables the transmission of data on the selected STOP TX ENDPOINT endpoint. After issuing the command, ﬂush the corresponding endpoint FIFO; see Section 32.7.4, “USB Command Register (USCOM).”...
Page 862: Programming The Usb Host Controller
B and subsequent revisions of the MPC850. Earlier revisions support only high-speed (12 Mbps) host operation. The MPC850 implementation of a USB host uses endpoint 0 to control the host transmission and reception. The other endpoints are typically not used, unless for testing purposes (loop-back).
Page 863: Usb Host Controller Initialization Example
Programming the USB Host Controller • For low-speed transactions with an external hub, set TxBD[LSP] in the token’s BD. This causes the USB host controller to generate a preamble (PRE token) at full speed before changing the transmit rate to low speed and sending the data packet. After completion of the transaction, the host returns to full-speed operation.
Page 864: Usb Function Controller Initialization Example
It can be used to set up four function endpoints (0–3) to ﬁll transmit FIFOs so that data is ready for transmission when an IN token is received from the USB. The token can be generated using a USB trafﬁc generator. MPC850 Family User’s Manual...
Page 865 USB Function Controller Initialization Example 1. Assuming BRG1 is the clock source (SICR[R1CS] = 0b000), write 0x0001_0000 to BRGC1 for division factor 1 to produce 48 MHz. This also assumes that the system clock is 48 MHz. 2. Clear PADIR[14,15] and set PAPAR[14,15] to select USBRXD and USBOE. 3.
Page 866 36. Write 0x82 to USCOM to start ﬁlling the Tx FIFO with endpoint 2 data ready for transmission when an IN token is received. 37. Write 0x83 to USCOM to start ﬁlling the Tx FIFO with endpoint 3 data ready for transmission when an IN token is received. MPC850 Family User’s Manual...
Page 867 Chapter 33 C Controller The inter-integrated circuit (I C®) controller lets the MPC850 exchange data with other C devices, such as microcontrollers, EEPROMs, real-time clock devices, A/D converters, and LCD displays. The I C controller uses a synchronous, multimaster bus that can connect several integrated circuits on a board.
Page 868: I2C Features
When the I C controller is a slave, the SCL clock input shifts data in and out through SDA. The SCL frequency can range from DC to BRGCLK/48. MPC850 Family User’s Manual...
Page 869: I2C Controller Transfers
Initialize the ﬁrst transmit data byte with the slave address and write request (R/W = 0). If the MPC850 is the slave target of the write, prepare receive buffers and BDs to await the master’s request. Figure 33-4 shows the timing for a master write.
Page 870 33.3.3 I C Master Read (Slave Write) Before initiating a master read with the MPC850, prepare a transmit buffer of size bytes, where is the number of bytes to be read from the slave. The ﬁrst transmit byte should be initialized to the slave address with R/W = 1. The next transmit bytes are used strictly for timing and can be left uninitialized.
Page 871 2. The slave detects a start condition on SDA and SCL. 3. After the ﬁrst byte is shifted in, the slave compares the received data to its slave address. If the slave is an MPC850, the address is programmed in its I C address register (I2ADD).
Page 872: I2C Registers
Problems could also arise if the MPC850's I C controller master sets up a transmit buffer and BD for a write request, but then is the target of a read request from another master.
Page 873 I2C Registers Table 33-1. I2MOD Field Descriptions (Continued) Bits Name Description 5–6 PDIV Predivider. Selects the clock division factor before it is input into the I C BRG. The clock source for the C BRG is the BRGCLK generated by the SIU. 00 BRGCLK/32 01 BRGCLK/16 10 BRGCLK/8...
Page 874 Rx buffer. Set after the last character is written to the Rx buffer and the RxBD is closed. 33.4.5 I C Command Register (I2COM) The I C command register, shown in Figure 33-10, is used to start I C transfers and to select master or slave mode. MPC850 Family User’s Manual...
Page 875: I2C Parameter Ram
I2C Parameter RAM Field — Reset 0000_0000 Addr 0x86C Figure 33-10. I C Command Register (I2COM) Table 33-5 describes I2COM ﬁelds. Table 33-5. I2COM Field Descriptions Bits Name Description Start transmit. In master mode, setting STR causes the I C controller to start sending data from the C Tx buffers if they are ready.
Page 876 Normally, these parameters need not be accessed. Figure 33-11 shows the RFCR/TFCR bit ﬁelds. AT[1–3] Field — Reset 0000_0000 Addr I2C Base + 04 (RFCR)/I2C Base + 05 (TFCR) Figure 33-11. I C Function Code Registers (RFCR/TFCR) MPC850 Family User’s Manual...
Page 877: I2C Commands
I2C Commands Table 33-7 describes the RFCR/TFCR bit ﬁelds. Table 33-7. RFCR/TFCR Field Descriptions Bits Name Description 0–22 — Reserved, should be cleared. 3–4 Byte ordering. Set BO to select the required byte ordering for the buffer. If BO is changed on-the-ﬂy, it takes effect at the beginning of the next frame (Ethernet, HDLC, and transparent) or at the beginning of the next BD.
Page 878: I2C Buffer Descriptor (Bd) Tables
It closes the buffer when a stop or start condition is found on the I C bus or when an overrun error occurs. The core should write RxBD bits before the I C controller is enabled. MPC850 Family User’s Manual...
Page 879: I 2 C Buffer Descriptors (Bds)
I2C Buffer Descriptor (BD) Tables Offset + 0 — — — Offset + 2 Data Length RX Buffer Pointer Offset + 4 Offset + 6 Figure 33-13. I C Receive Buffer Descriptor (RxBD) Table 33-9 describes I C RxBD status and control bits. Table 33-9.
Page 880 The I C controller updates UN after the buffer is sent. Collision. Indicates that transmission terminated because the transmitter was lost while arbitrating for the bus. The I C controller updates CL after the buffer is sent. MPC850 Family User’s Manual...
Page 881: Features
To support ﬂexible conﬁguration of the CPM, many dedicated peripheral functions are multiplexed onto ports A, B, C, and D. Functions are grouped to maximize the signals’ usefulness to the greatest number of MPC850 applications. To understand signal assignments described in this chapter, it helps to understand each CPM peripheral.
Page 882 PADAT is also stored in the output latch but cannot reach the port signal, so when PADAT is read, the signal’s state is read. If an input to a peripheral is not supplied from a signal, the default value listed in Table 34-1 is supplied. MPC850 Family User’s Manual...
Page 883: Port A Registers
Port A 34.2.1 Port A Registers Port A has four memory-mapped control registers, described in the following sections. 34.2.1.1 Port A Open-Drain Register (PAODR) The port A open-drain register (PAODR), shown in Figure 34-1, determines which port signals with serial channel output capability are conﬁgured in a normal or wired-OR conﬁguration.
Page 884: Port A Data Direction Register (Padir)
— DD4 DD5 DD6 DD7 DD8 DD9 — — DD12 DD13 DD14 DD15 Reset — — — — — — R/W R/W R/W R/W R/W R/W Addr 0x952 Figure 34-4. Port A Pin Assignment Register (PAPAR) MPC850 Family User’s Manual...
Page 885: Port A Functional Block Diagrams
Port A Table 34-5 describes PAPAR bits. Table 34-5. PAPAR Bit Descriptions Bits Name Description 0–3, — Reserved 10–11 4–9, Conﬁgures a signal for general-purpose I/O or for dedicated peripheral function 12–15 0 General-purpose I/O. The peripheral functions of the signal are not used. 1 Dedicated peripheral function.
Page 886 Read Path To PADAT[14] Write Path From USBRXD/PA14 PADAT[14] Open Drain Output Control Latch 16-Bits PADIR 16-Bits USBTXD From USB PAODR 16-Bits PAPAR Figure 34-6. Block Diagram for PA14 (True for all Open-Drain Port Signals) MPC850 Family User’s Manual...
Page 887 Port B 34.3 Port B All port B signals can be open-drain. They are conﬁgured independently as general-purpose I/O signals if the corresponding bit in the PBPAR is cleared and they are conﬁgured as dedicated on-chip peripheral signals if the corresponding PBPAR bit is set. When conﬁgured as a general-purpose I/O signal, the signal direction of that signal is determined by the corresponding control bit in the PBDIR.
Page 888: The Port B Registers
0 The I/O signal is actively driven as an output. 1 The I/O signal is an open-drain driver. As an output, the signal is actively driven low. Otherwise, it is three-stated. Note that SMTXD1 cannot be conﬁgured as an open-drain driver, regardless of PBODR[OD25]. MPC850 Family User’s Manual...
Page 889: Port B Data Register (Pbdat)
Port B 34.3.1.2 Port B Data Register (PBDAT) Reading the port B data register (PBDAT) returns data to the signal, regardless of whether it is an input or output. This allows output conﬂicts to be found on the signal by comparing the written data with the data on the signal.
Page 890: Port B Pin Assignment Register (Pbpar)
— — — Addr 0xABC Bits Field DD16 DD17 DD18 DD19 — — DD22 DD23 DD24 DD25 DD26 DD27 DD28 DD29 DD30 DD31 Reset — — Addr 0xABE Figure 34-10. Port B Pin Assignment Register (PBPAR) MPC850 Family User’s Manual...
Page 891 Port C Table 34-10 describes PBPAR bits. Table 34-10. PBPAR Bit Descriptions Bits Name Description 0–15, — Reserved 20–21 16–19, Port assignment. Determines whether a signal is conﬁgured for general-purpose I/O or dedicated 22–31 peripheral function. 0 General-purpose I/O. The peripheral functions of the signal are not used. 1 Dedicated peripheral function.
Page 892 SCC internally but can also generate interrupts. Port C still detects changes on CTS and CD and asserts the corresponding interrupt request, but the SCC simultaneously uses CTS and/or CD to control operation automatically. This allows MPC850 Family User’s Manual...
Page 893: Port C Registers
Port C the implementation of V.24, X.21, and X.21 bis protocols with help from other general-purpose I/O signals. To conﬁgure a port C signal as a CTS or CD signal that connects to the SCC and generates interrupts, follow these steps: 1.
Page 894: Port C Data Direction Register (Pcdir)
The port C pin assignment register (PCPAR) conﬁgures signals as general-purpose I/O or dedicated for use with a peripheral. Field — DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15 Reset 0000_0000_0000_0000 Addr 0x962 Figure 34-13. Port C Pin Assignment Register (PCPAR) MPC850 Family User’s Manual...
Page 895: Port C Special Options Register (Pcso)
Port C Table 34-14 describes PCPAR bits. Table 34-14. PCPAR Bit Descriptions Bits Name Description 0–3 — Reserved. 4–15 Conﬁgures a signal for general-purpose I/O or for dedicated peripheral function 0 General-purpose I/O. The peripheral functions of the signal are not used. 1 Dedicated peripheral function.
Page 896: Port C Interrupt Control Register (Pcint)
The port I/O signal is conﬁgured as an input if the corresponding bit in the port D data direction register (PDDIR) is cleared and as an output if the bit is set. PDPAR and PDDIR are cleared at system reset, which conﬁgures all port D signals as general-purpose inputs. MPC850 Family User’s Manual...
Page 897: Port D Registers
PORT D3 — — Specialized versions of the MPC850 multiplex the port D signals with other functions, such as an ATM UTOPIA interface or 100BASE-T MII (media-independent interface). See the speciﬁc part’s supplementary documentation for details. JAN LOOK 34.5.1 Port D Registers Port D has three memory-mapped, read/write control registers.
Page 898: Port D Pin Assignment Register (Pdpar)
34.5.1.3 Port D Pin Assignment Register (PDPAR) The port D pin assignment register (PDPAR) conﬁgures signals as general-purpose I/O or dedicated for use with a peripheral. Field — DD3–DD15 Reset 0000_0000_0000_0000 Addr 0x972 Figure 34-18. Port D Pin Assignment Register (PDPAR) MPC850 Family User’s Manual...
Page 899 Port D Table 34-20 describes PDPAR bits. Table 34-20. PDPAR Bit Descriptions Bits Name Description 0–2 — Reserved and must be cleared. Note that setting bits 0 or 1 causes erratic behavior resulting in CPM lockup. 3–15 Conﬁgures a signal for general-purpose I/O or for dedicated peripheral function 0 General-purpose I/O.
Page 900 Port D MPC850 Family User’s Manual...
Page 901: Features
CPIC-managed interrupt sources are prioritized and bits are set in the CPM interrupt pending register (CIPR). Figure 35-1 shows the MPC850 interrupt structure. The left of the ﬁgure shows individual interrupt sources managed by the CPIC, which signals CPIC-managed interrupts to the SIU, shown in the middle of Figure 35-1.
Page 902 Level 0 Debug Debug Figure 35-1. MPC850 Interrupt Structure Although all CPM interrupts are presented to the SIU at the same priority level (speciﬁed in CICR[IRL]), individual CPM interrupt sources are prioritized as described in Section 35.2, “CPM Interrupt Source Priorities.” The MPC850provides limited ability to reorder the interrupt priorities of the USB and SCCs and to specify the highest priority interrupt source.
Page 903: Cpm Interrupt Source Priorities
CPM Interrupt Source Priorities 35.2 CPM Interrupt Source Priorities The CPIC has 27 interrupt sources that assert a single programmable interrupt request level to the core. Default interrupt priorities are as shown in Table 35-1. Table 35-1. Prioritization of CPM Interrupt Sources Multiple Multiple Priority...
Page 904: Highest Priority Interrupt
Section 35.5.3, “CPM Interrupt Mask Register.” When a masked source requests an interrupt, the corresponding CIPR bit is set but the CPIC does not signal the interrupt to the core. Masking all sources allows the implementation of a polling interrupt servicing scheme. MPC850 Family User’s Manual...
Page 905: Generating And Calculating Interrupt Vectors
Generating and Calculating Interrupt Vectors CPM sub-blocks with multiple interrupting events can be masked individually by programming a mask register within that block (such as the SMC UART register (SMCM), described in Section 30.3.12, “SMC UART Event Register (SMCE)/Mask Register (SMCM)”).
Page 906: Cpic Registers
• CPM interrupt mask register (CIMR)—Can be used to mask CPM interrupt sources. • CPM interrupt in-service register (CISR)—Allows nesting interrupt requests within the CPM interrupt level. Note that the names and placement of bits is identical in the CIPR, CIMR, and CISR. MPC850 Family User’s Manual...
Page 907: Cpm Interrupt Configuration Register (Cicr)
CPIC Registers 35.5.1 CPM Interrupt Conﬁguration Register (CICR) The CPM interrupt conﬁguration register (CICR) deﬁnes CPM interrupt request levels, the priority between the USB and SCCs, and the highest priority interrupt. Field — —SCdP —SCcP —SCbP —SCaP Reset 0000_0000_0000_0000 Address 0x940 Field —...
Page 908: Cpm Interrupt Pending Register (Cipr)
In a polled interrupt scheme, the user must periodically read the CIPR. To avoid losing subsequent events from the same interrupt source, acknowledge an interrupt before actually handling it in the service routine. Acknowledge interrupts from port C by clearing the CIPR MPC850 Family User’s Manual...
Page 909: Cpm Interrupt Mask Register
CPIC Registers bit directly (by writing ones). For all other interrupt sources, however, clear the unmasked event register bits instead, thus causing the CIPR bit to be cleared. The USB and SCCs CIPR bit positions are not changed according to their relative priority (as determined by CICR[SCxP] and CICR[SPS]).
Page 910: Interrupt Handler Example—Single-Event Interrupt Source
The following steps show how to handle an interrupt source without multiple events. 1. Set CIVR[IACK]. 2. Read CIVR[VN] to determine the vector number for the interrupt handler. 3. Handle the interrupt event indicated through the port C6 signal. 4. Clear CISR[PC6]. 5. Execute the rfi instruction. MPC850 Family User’s Manual...
Page 911: Interrupt Handler Example—Multiple-Event Interrupt Source
6. Clear CISR[SCC2]. 7. Execute the rfi instruction. If any unmasked SCCE bits remain (either not cleared by the software or set by the MPC850 during the execution of this handler), this interrupt source is pending again immediately after the rfi instruction.
Page 912 Interrupt Handler Example—Multiple-Event Interrupt Source MPC850 Family User’s Manual...
Page 913: Atm Parameter Ram
Appendix F. It assumes a basic understanding of the PowerPC exception model, the MPC850 interrupt structure, the MPC850 communications processor module (CPM) with a particular emphasis on the SCC, as well a working knowledge of ATM. A complete discussion of these protocols is beyond the scope of this book.
Page 914 Table i contains acronyms and abbreviations used in this document. Note that the meanings for some acronyms (such as SDR1 and DSISR) are historical, and the words for which an acronym stands may not be intuitively obvious. MPC850 Family User’s Manual...
Page 915 Table vii. Acronyms and Abbreviated Terms Term Meaning ATM adaptation layer AAL5 CPCS–PDU Available bit rate Allowed cell rate Arithmetic logic unit ATM pace control Asynchronous transfer mode Buffer descriptor Bit interleaved parity BIST Built-in self test Backward reporting cells Burst tolerance Constant bit rate Content-addressable memory...
Page 916 Joint Test Action Group JTAG Joint Test Action Group Local area network LIFO Last-in-ﬁrst-out Least recently used Least-signiﬁcant byte Least-signiﬁcant bit Multiply accumulate or media access control Maximum burst size Media-independent interface Most-signiﬁcant byte Most-signiﬁcant bit Machine state register MPC850 Family User’s Manual...
Page 917 Table vii. Acronyms and Abbreviated Terms (Continued) Term Meaning Not a number NCITS Number of cells in a time slot Network interface card Network interface unit NMSI Nonmultiplexed serial interface Non-real time Open systems interconnection Peripheral component interconnect Protocol data unit Peak cell rate Physical layer Performance monitors...
Page 918 Virtual channel or circuit or call or connection Virtual channel connection Virtual circuit identiﬁer Virtual path Virtual path connection Virtual path identiﬁer Universal serial bus UTOPIA Universal test and operations physical interface for ATM Virtual channel or virtual circuit Wide area network MPC850 Family User’s Manual...
Page 919: Atm Controller
• Bridging and routing applications 36.2 MPC850SR and MPC850 Differences The MPC850SR is pin-compatible with the standard MPC850 (non-ATM), and they have identical electrical and mechanical speciﬁcations. However, when running an ATM application, the MPC850SR loses some functionality due to internal resource conﬂicts.
Page 920: Idma2 Restriction
ABR services. • Supports UTOPIA and serial (E1/T1/xDSL) interfaces. • Compliant with ATM Forum UNI 4.0 speciﬁcation. • CLP and congestion indication marking in RxBD. • Separate transmit and receive buffer descriptor (BD) tables for each channel. MPC850 Family User’s Manual...
Page 921 ATM Features • Interrupt reporting optionally enabled per channel • Supports 53-byte to 64-byte (expanded) ATM cell size. • Glueless serial interface to an xDSL interface device. • Supports AAL5 connections: — Reassembly: – Reassembles CPCS_PDU directly to host memory –...
Page 922: Atm Pace Control
36.5 Overview of ATM Operation The MPC850SR supports ATM adaptation layers AAL0 and AAL5 segmentation and reassembly and the ATM layer for the convergence sublayer (CS). User data resides in system memory in single or multiple data buffers. MPC850 Family User’s Manual...
Page 923: Utopia Operation
UTOPIA Operation There are two physical layer/interface modes of operation: a UTOPIA interface and a serial interface. In UTOPIA mode, the ATM layer directly interfaces to the PHY through the UTOPIA interface. In serial mode, the ATM controller also implements the transmission convergence (TC) sublayer and interfaces to the PHY layer through the SCCs.
Page 924: Utopia Receive Overview
For AAL0, the ATM controller copies the cell (except the HEC) from the UTOPIA interface to the channel’s current buffer and optionally performs a CRC10 check on the cell payload. The CRC10 option is used to support OAM cell checking (by host software) according to the ITU speciﬁcation I.610. MPC850 Family User’s Manual...
Page 925: Expanded Cells
Serial ATM Operation NOTE: The received HEC is not checked by the ATM controller in UTOPIA mode; it is the responsibility of the PHY to check the HEC and discard cells with an incorrect HEC. 36.6.3 Expanded Cells An option for supporting ATM cells larger than the standard 53 bytes (4-byte header, 1-byte HEC and 48-byte payload) is available when operating in UTOPIA mode.
Page 926: Serial Atm Transmit Overview
(CAM). If the header has no match the incoming cell is treated as an AAL0 cell, and is passed to the global raw cell queue (channel 0). If the cell is matched to a channel the channel status is read from the receive connection table (RCT). MPC850 Family User’s Manual...
Page 927: Cell Delineation
Serial ATM Operation As the FIFO of the SCC ﬁlls, the received cell is read from the FIFO, the HEC is checked, and the cell is optionally descrambled. Cells with HEC errors are passed to the global raw cell queue, and the HEC error is recorded in the BD. The receiver screens out either idle cells or unassigned cells as programmed.
Page 928: Atm Pace Control (Apc)
The overall throughput depends on the number of external channels and the bit rate ratio between external and internal channels; that is, higher bit rate channels should be assigned internal channel numbers. MPC850 Family User’s Manual...
Page 929: Atm Buffer Descriptors (Bds)
Chapter 37 Buffer Descriptors and Connection Tables The communications processor module (CPM) manages ATM trafﬁc through the UTOPIA and serial interfaces by means of transmit and receive buffer descriptors (BDs) and transmit and receive connection tables (TCTs and RCTs). The BDs are grouped into circular tables of pointers into the data buffer space in external memory.
Page 930: Aal5 Buffers
Note that AAL5 transmit buffers have no alignment restrictions. Receive buffers, however, must start on a burst-aligned address (divisible by 16) and their lengths should be a multiple of 48 bytes (that is, the value of SMRBLR in the SCC MPC850 Family User’s Manual...
Page 931: Aal0 Buffers
ATM Buffer Descriptors (BDs) parameter RAM should be a multiple of 48). The buffers are ﬁlled with multiples of 48 bytes, except for the last buffer in a frame from which the AAL5 pads are removed. 37.1.2 AAL0 Buffers AAL0 buffers contain one raw cell. When the receiver or transmitter completes writing or reading the buffer, it moves to the next BD in the AAL0 channel’s BD table in preparation for the next transfer and optionally issues an interrupt.
Page 932 OFFSET + C CELL HEADER EXPANSION 1 OFFSET + 10 CELL HEADER EXPANSION 2 OFFSET + 14 CELL HEADER EXPANSION 3 Figure 37-4. ATM RxBD in Expanded Cell Mode (UTOPIA Only) Table 37-1 describes the ATM RxBD ﬁelds. MPC850 Family User’s Manual...
Page 933 ATM Buffer Descriptors (BDs) Table 37-1. ATM RxBD Field Descriptions Offset from Bits Name Description RBD_PTR 0x00 Empty. Determines whether a buffer is accessible by the CPU core or the CP. 0 The data buffer associated with this RxBD has been ﬁlled with the received data, or data reception has been aborted due to an error condition.
Page 934 ﬁelds. This ﬁeld is taken from the frame trailer, and contains user-to-user (UU) information and common part indications (CPI). This ﬁeld is written by the CP and is valid only for the last BD in the AAL5 frame. MPC850 Family User’s Manual...
Page 935: Atm Transmit Buffer Descriptors (Txbds)
ATM Buffer Descriptors (BDs) Table 37-1. ATM RxBD Field Descriptions (Continued) Offset from Bits Name Description RBD_PTR 0x0A — — Reserved, should be cleared. 0x0C — Cell header Cell header expansion 1, 2, and 3 (UTOPIA expanded cell mode only). These expansion 1, ﬁelds are added to the BD when expanded cells are enabled (SRSTATE[EC] 2, and 3...
Page 936 CP. 0x04 — Transmit data Contains the address of the associated data buffer. The buffer may reside in buffer pointer either internal or external memory. This value is not modiﬁed by the CP. MPC850 Family User’s Manual...
Page 937: Receive And Transmit Connection Tables(Rcts And Tcts)
Receive and Transmit Connection Tables (RCTs and TCTs) Table 37-2. ATM TxBD Field Descriptions (Continued) Offset from Bits Name Description TBD_PTR 0x08 — CPCS-UU and CPCS-UU and CPI (AAL5 only and RH = 0 and L = 1). Valid only when the current BD is the last BD of an AAL5 frame.
Page 938: Receive Connection Table (Rct)
CT_Offset + A CT_Offset + C RTMLEN CT_Offset + E RBD_PTR CT_Offset + 10 RBASE CT_Offset + 12 TSTAMP CT_Offset + 14 IMASK CT_Offset + 16 — CT_Offset + 1F Figure 37-8. Receive Connection Table (RCT) MPC850 Family User’s Manual...
Page 939: Atm Exceptions
Receive and Transmit Connection Tables (RCTs and TCTs) Table 37-3 describes the RCT ﬁelds. Table 37-3. RCT Field Descriptions CT Offset Bits Name Description 0x00 FHNT Frame hunt mode. Indicates that this channel has had a busy exception or a restart and is currently in frame hunt mode.
Page 940: Transmit Connection Table (Tct)
0x16–0x1F — — Reserved, should be cleared. 37.2.2 Transmit Connection Table (TCT) Each TCT holds parameters (channel conﬁguration, pointers, status ﬂags, and temporary data) for a single ATM transmit channel. Figure 37-9 shows the TCT structure. MPC850 Family User’s Manual...
Page 941 Receive and Transmit Connection Tables (RCTs and TCTs) CT_Offset + 20 — — — — — — — — — — CR10 CDIS CT_Offset + 22 TBALEN CT_Offset + 24 TCRC CT_Offset + 28 TB_PTR CT_Offset + 2C TTMLEN CT_Offset + 2E TBD_PTR CT_Offset + 30 TBASE...
Page 942 Initialize this ﬁeld with 0xFFFF to indicate the end of the linked list. 0x3A — APCPR APC pace remainder. Contains the remainder of the rate generated by the APC after adding the pace FRACTION to the cumulative APCPR. Should be cleared during initialization. MPC850 Family User’s Manual...
Page 943 Receive and Transmit Connection Tables (RCTs and TCTs) Table 37-4. TCT Field Descriptions (Continued) CT Offset Bits Name Description 0x3C APC out. Can be used as a completion ﬂag for the TRANSMIT DEACTIVATE CHANNEL command. When the command is issued, OUT is TRANSMIT DEACTIVATE CHANNEL immediately set.
Page 944 Receive and Transmit Connection Tables (RCTs and TCTs) MPC850 Family User’s Manual...
Page 945: Atm Parameter Ram
Chapter 38 ATM Parameter RAM The SCC parameter RAM is used to conﬁgure the SCCs for serial ATM and the UTOPIA interface. The CP also uses parameter RAM to store operational and temporary values used during SAR activities. When ATM operations are performed, the SCC parameter RAM is mapped as shown in Table 38-1, Table 38-2, and Table 38-2.
Page 946 TSTA ﬁeld to the RCT when a new frame is received. TSTA should be initialized with a value equal to (TM_BASE + 4*timer number). 0x3C OLDLEN Hword Transmitter temporary length. Do not write to this location. MPC850 Family User’s Manual...
Page 947 Table 38-1. Serial ATM and UTOPIA Interface Parameter RAM Map (Continued) Offset Name Width Description SMRBLR 0x3E Hword SAR maximum receive buffer length register. Determines the number of bytes the CP writes to a receive buffer before moving to the next buffer. SMRBLR is user-deﬁned and should be a multiple of 48 bytes.
Page 948 HEC error counter. Contains a 16-bit counter for incoming cells with HEC errors. HEC_ERR may be read by the user at any time. Should be cleared during initialization. 0xD2 — Hword Reserved RSCRAM 0xD4 Word Receiver scrambling storage. Should be cleared during initialization. RSCRAM1 0xD8 Word MPC850 Family User’s Manual...
Page 949: Sar Receive Function Code Register (Srfcr)
SAR Receive Function Code Register (SRFCR) Table 38-2. Serial ATM Parameter RAM Map (Continued) Offset Name Width Description 0xDC TSCRAM Word Transmitter scrambling storage. Should be cleared during initialization. TSCRAM1 0xE0 Word 0xE4 RCRC Word Receiver temporary CRC 0xE8 TCRC Word Transmitter temporary CRC 0xEC...
Page 950: Sar Receive State Register (Srstate)
UTOPIA port. It must not be written to while the UTOPIA port is operating. 0 Receive enabled. 1 Receive disabled. ATM physical interface type 0 UTOPIA PHY 1 Serial PHY MPHY Multiple PHY operation. Valid only in UTOPIA mode. 0 Single PHY mode 1 Multiple PHY mode MPC850 Family User’s Manual...
Page 951: Sar Transmit Function Code Register (Stfcr)
SAR Transmit Function Code Register (STFCR) 38.3 SAR Transmit Function Code Register (STFCR) The SAR transmit function code register (STFCR), shown in Figure 38-3, contains the user-initialized function codes and byte ordering information for DMA transfers. FIELD — RESET — —...
Page 952: Address Match Parameters (Am1–Am5)
• Content-addressable memory (CAM)—See Table 38-11 for the AM1–AM5 conﬁguration for CAM operation. The address match parameter configuration when using the internal address look-up table (EXT = 0) is shown in Table 38-7. See also Section 39.1.1, “Internal Look-up Mechanism (SRSTATE[EXT] = 0).” MPC850 Family User’s Manual...
Page 953 Address Match Parameters (AM1–AM5) Table 38-7. AM1–AM5 Parameters for the Internal Look-up Table Field Name Function HMASK Header mask. The ATM controller masks the header of each incoming cell with HMASK and uses the resulting masked header in the address match process. The masking process uses a bitwise AND function so bits are masked out by clearing the relevant bits in HMASK.
Page 954 The address match parameter configuration for extended channel mode CAM operation (EXT = 1 and ACP = 0) is shown in Table 38-11. See also the discussion in Section 39.1.3, “CAM Address Mapping (SRSTATE[EXT,ACP] = 10).” MPC850 Family User’s Manual...
Page 955: Apc State Register (Apcst)
APC State Register (APCST) Table 38-11. AM1–AM5 Parameters for Extended Channel CAM Operation Field Name Function HMASK Header mask. The ATM controller masks the header of each incoming cell with HMASK and uses the resulting masked header for address matching. The masking process uses a bitwise AND function so bits are masked out by clearing the relevant bits in HMASK.
Page 956: Serial Cell Synchronization Status Register (Astatus)
Receiver FIFO overrun. The CP sets this ﬂag to indicate a receiver overrun event has occurred. The user can acknowledge the ﬂag by clearing it. 0 No receiver FIFO overrun 1 Receiver FIFO overrun. Note that the SCCE[GOV] bit is also set. MPC850 Family User’s Manual...
Page 957: Serial Cell Synchronization Status Register (Astatus)
Serial Cell Synchronization Status Register (ASTATUS) Table 38-13. ASTATUS Register Field Descriptions (Continued) Bits Name Description URUN Transmitter FIFO underrun. The CP sets this ﬂag to indicate a transmitter underrun event has occurred. The user can acknowledge the ﬂag by clearing it. 0 No transmitter FIFO underrun 1 Transmitter FIFO underrun.
Page 958 Serial Cell Synchronization Status Register (ASTATUS) MPC850 Family User’s Manual...
Page 959: Address Mapping
Chapter 39 ATM Controller This chapter describes the address mapping mechanisms of the ATM controller to support connection tables for both single- and multi-PHY interfaces, and the commands provided to control ATM transmit and receive operations on a channel-by-channel basis. 39.1 Address Mapping Three methods for mapping incoming cell header addresses to local ATM channel numbers are available.
Page 960: Adding A New Internal Channel
The address compression mechanism uses two levels of address translation to help minimize the memory space needed to cover the available address range. In the ﬁrst-level compression, the GFC, VPI, and PTI ﬁelds of the received header are masked with MPC850 Family User’s Manual...
Page 961: First-Level Addressing Table (Flt)
Address Mapping FLMASK to create a pointer (offset from FLBASE) to the ﬁrst-level addressing table. The ﬁrst-level table (FLT) contains an additional mask and table pointer to one of the second-level tables (SLTs), referred to as the second-level table offset (SLTOFFSET). (SLTOFFSET is an offset from the base address of the second-level tables (SLBASE).
Page 962: Address Compression Example
ﬁrst- and second-level address masking procedure are checked for non-zero values. If a non-zero value is found, the cell is passed to the global raw cell queue. See Table 38-11 for a description of the CUMB bit. MPC850 Family User’s Manual...
Page 963: Oam Screening
Multi-PHY Conﬁguration (MPHY) Note that if CUMB is set, the user should also include the PTI bits in FLMASK so that cells marked as congested (EFCI = 1) or last (PTI[1] =1) in the PTI are not received into the global raw cell queue.
Page 964: Receive Multi-Phy Operation
Global raw cell queue offset AMEND1 AMBASE1 APBASE1 Global raw cell queue offset AMEND2 AMBASE2 APBASE2 Global raw cell queue offset AMEND3 AMBASE3 APBASE3 Global raw cell queue offset Figure 39-4. Address Mapping Tables for Multi-PHY Operations MPC850 Family User’s Manual...
Page 965: Address Compression Multi-Phy Support
ATM Commands Note that the address in the AMEND ﬁeld is common to the four look-up tables. AMEND points to the highest valid channel number in any one of the four tables. For example, if PHY3 handles 5 channels and the other PHYs handle only 2 channels, the address in AMEND should be set to point to the ﬁfth channel of PHY3.
Page 966 1x Reserved Command semaphore ﬂag. Set by the core and cleared by the CP. 0 CP is ready for a new command. 1 CP is currently processing a command—cleared when the command is done or after reset. MPC850 Family User’s Manual...
Page 967 ATM Commands The ATM commands are described in Table 39-2. Table 39-2. ATM Commands Command Description Opcode Activates the channel speciﬁed in COMM_CH by inserting its channel number into the TRANSMIT ACTIVATE APC scheduling table at the location indicated by the service pointer. The channel CHANNEL most recently inserted is the ﬁrst to be chosen by the APC.
Page 968 ATM Commands MPC850 Family User’s Manual...
Page 969: Apc Algorithm
Chapter 40 ATM Pace Control The ATM layer performs cell multiplexing and demultiplexing. The ATM pace control unit (APC) is part of the ATM cell multiplexing process. The APC processes the trafﬁc parameters of each channel and deﬁnes the multiplex timing for all the channels. Cell multiplexing is done by the transmitter according to the trafﬁc control function implemented by the APC.
Page 970: Apc Implementation
(APCT_SPTRx). If more than NCITS channel numbers are scheduled for the same time slot, the leftover channel numbers remain pending until the next time the APC is activated. The lagging APCT_SPTRx service pointer keeps track of the pending channels so that cells are only deferred, not dropped. MPC850 Family User’s Manual...
Page 971: Apc Parameters
APC Algorithm If the highest priority APC level cannot provide NCITS cells, the APC begins traversing the lower priority APC levels hunting for additional channels (advancing each APC level’s service pointer in turn) until a total of NCITS cells are found or until no APC levels remain. However, because traversing the APC levels could potentially cause too much delay, the APC_MI (maximum iteration) parameter is provided to limit the total number of times the APC advances a service pointer.
Page 972: Programming Apc Scheduling Table Size And Ncits
APC timeout will vary around the average deﬁned by NCITS. For example, if NCITS were programmed to 2.5, then 2 cells would be scheduled during one iteration of the APC algorithm, followed by 3 cells the next time, followed by 2, and so on. MPC850 Family User’s Manual...
Page 973: Programming Rates For Channels
APC Algorithm 40.1.4 Deﬁning APC Slot Time The APC deﬁnes the maximum bit rate of the cell scheduler through the period of the APC timer tick and the number of cells scheduled per APC timer tick (NCITS). The period of the APC timer is referred to as an APC time slot.
Page 974: Apc Initialization And Operating Considerations
APC scheduling table. This can effectively be implemented by activating channels (using the command) at random TRANSMIT CHANNEL ACTIVATE intervals, such that they are not all written to the same APC scheduling table entry. MPC850 Family User’s Manual...
Page 975: Direct Scheduling Of Cells
Direct Scheduling of Cells 40.2 Direct Scheduling of Cells The ATM controller implements an command to allow the user to insert a APC BYPASS channel number directly into the transmit queue on a cell-by-cell basis. This command can be used at any time in either serial mode or UTOPIA mode to insert a single cell for a channel into the transmit queue, with no direct transmit queue pointer manipulation required.
Page 976: Using The Apc Without Using Utopia
APCST parameter on parameter page 4. Therefore, the APCST parameter on parameter page 4 must always be valid, even if the controller associated with parameter page 4 (that is, the UTOPIA port) is not used in ATM mode. MPC850 Family User’s Manual...
Page 977: Apc Scheduling Tables
APC Scheduling Tables If the UTOPIA port is not used, the APCST parameter on parameter page 4 must indicate that the APC on page 4 is disabled and must also point to the active APC page(s). This is accomplished using the APCST[NSER,CSER] mechanism described in Section 40.3, “Using the APC with Multiple ATM Ports.”...
Page 978: Phy Transmit Queues
APC scheduling table ﬁrst priority APCT_BASE1 value service pointer. See Table 40-2.. 0x08–0x0F — Reserved APC_MI 0x10 Half Word APC—Max iteration User deﬁned NCITS 0x12 Half Word Number of cells in time slot. See User deﬁned Table 40-2. MPC850 Family User’s Manual...
Page 979 APC Priority Levels Table 40-1. APC Priority Levels (Continued) Offset Name Width Description User Writes 0x14 APCNT Half Word APC—N timer 0000 0x16-ox1F — Reserved (n * 0x20) + 0x0 APCT_BASEn Half Word APC scheduling table base pointer User deﬁned for the N’th priority APC level (n * 0x20) + 0x2 APCT_ENDn...
Page 980 APC routine, thereby avoiding excessive APC latency. The recommended value for APC_MI is equal to the minimum value of TCT[APCP] (APC pace) of all channels, and should not exceed 32. MPC850 Family User’s Manual...
Page 981 Chapter 41 ATM Exceptions Interrupt handling for ATM channels involves two principle data structures: an event register (SCCE or IDSR1) and a circular ATM interrupt queue. The interrupt queue (one per controller) is shown in Figure 41-1. 32 Bits INTBASE V = 0 W = 0 V = 0...
Page 982: Atm Event Registers
Global interrupt. Indicates that at least one new entry has been added to the interrupt queue. After clearing the GINT event ﬂag, the host begins processing the entries using the service pointer. The host returns from the interrupt handler when it reaches an invalid queue entry (V = 0). MPC850 Family User’s Manual...
Page 983: Serial Atm Event Register (Scce)
ATM Event Registers Table 41-1. UTOPIA Event Register (IDSR1) Field Descriptions (Continued) Bits Name Description — Reserved — Reserved 41.1.2 Serial ATM Event Register (SCCE) The SCCE act as the ATM event register for serial mode and used to report events and generate interrupt requests.
Page 984: Interrupt Queue Entry
INTBASE. During initialization, the host should set the W bit only for the last entry of the queue. — Reserved MPC850 Family User’s Manual...
Page 985 Interrupt Queue Entry Table 41-3. Interrupt Queue Entry Field Descriptions (Continued) Name Description Congestion. Set by the CP when a congestion indication on a received cell (the middle bit of the PTI ﬁeld is set). This interrupt applies only to channels whose RCT[CNGI] is set. 4–7 —...
Page 986: Interrupt Queue Mask (Imask)
GINT global interrupt counter is not incremented. — — Figure 41-5. Interrupt Queue Mask (IMASK) Note that because the masking is performed in microcode, approximately 40 system clocks must elapse for a change in IMASK to take effect. MPC850 Family User’s Manual...
Page 987: Interface Conﬁguration
Chapter 42 Interface Conﬁguration The following sections describe the programming of registers and parameters for ATM operations through both the UTOPIA and serial interfaces. 42.1 General ATM Registers This section describes the general ATM registers. 42.1.1 Port D Pin Assignment Register (PDPAR) The ATM and UT bits have been added to the PDPAR register, shown in Figure 42-1.
Page 988: Utopia Interface
RISC Timer Table,” for additional information. 42.2 UTOPIA Mode Registers When operating in UTOPIA mode the PHY layer is connected to the MPC850 UTOPIA interface. The UTOPIA data signals and some of the control signals are connected to port D. The remaining UTOPIA control signals are connected to ports B and C. The UTOPIA mode requires several registers to be conﬁgured as described in the following sections.
Page 989 UTOPIA Mode Registers The frequency of the UTPCLK defaults to system frequency. The frequency ratio between the system clock and UTPCLK is an integer value (freq /freq = integer > 0). The utopia UTOPIA clock has a 50% duty cycle and is derived from the system frequency divided by two dividers.
Page 990: Port B Multiplexing
D signals are conﬁgured to support UTOPIA signals as shown in Table 42-3. The UTOPIA interface is described in Chapter 43, “UTOPIA Interface.” NOTE: Port D must be initialized before Port C to prevent the CPM from trying to use IDMA functionality. MPC850 Family User’s Manual...
Page 991: Utopia Mode Initialization
UTOPIA Mode Registers Table 42-3. Port D Pin Assignment PDPAR=1 Input to On-Chip Signal PDPAR = 0 UT=0 Peripherals UT=1 PDDIR=0 PDDIR=1 PD15 Port D15 — — UTPB[0] — PD14 Port D14 — — UTPB[1] — PD13 Port D13 — —...
Page 992: Serial Atm Mode Register (Psmr)
ATM mode register and controls both the scrambling and the HEC coset functions for the transmitter and receiver. FIELD — — SCRAM — — — — COSET — — — — — — — — RESET OPER ADDR Figure 42-3. Serial ATM Mode Register (PSMR) MPC850 Family User’s Manual...
Page 993 Serial ATM Conﬁguration Table 42-4 describes the PMSR serial ATM ﬁelds. Table 42-4. PSMR Serial ATM Field Descriptions Bits Name Description 0–1 — Reserved SCRAM Scrambling function during sending and receiving 0 = Disable cell payload scrambling. 1 = Enable cell payload scrambling. 3–6 —...
Page 994 Serial ATM Conﬁguration MPC850 Family User’s Manual...
Page 995: Mpc850Sr Utopia Interface Signals
UTOPIA support, and signal timing for single- and multi-PHY ATM operations. 43.1 MPC850SR UTOPIA Interface Signals The MPC850SR system bus signals are identical to the MPC850 signals described in the Chapter 12, “External Signals.” Additional signals are provided to support the UTOPIA interface operations.
Page 996 General-Purpose I/O Port D Bit 4—Bit 4 of the general-purpose I/O port D. UTPB[7] UTPB[7]—UTOPIA bus bit 7 input/output signal (most signiﬁcant bit of UTPB). PD[3] General-purpose I/O Port D Bit 3—Bit 3 of the general-purpose I/O port D. SOC—Start of cell input/output signal. MPC850 Family User’s Manual...
Page 997: Utopia Single-Phy
UTOPIA Single-PHY 43.2 UTOPIA Single-PHY The MPC850SR acts as an ATM layer UTOPIA master per the ATM Forum UTOPIA level 1 speciﬁcation for an ATM single-PHY conﬁguration. The MPC850SR implements the UTOPIA interface as an 8-bit wide bidirectional data bus using a cell-level handshake, and operates at frequencies up to 25 MHz.
Page 998: Receive Cell Transfer Operation
PHY asserted RxClav again to indicate that data was available. If the PHY is ready to send additional data at the end of the current data tenure, the PHY can assert RxClav at any time during the data transfer and hold RxClav asserted until the ﬁrst transfer the following data tenure. MPC850 Family User’s Manual...
Page 999: Transmit Cell Transfer Operation
UTOPIA Single-PHY UTPClk RxClav RxEnb UTPB Figure 43-3. UTOPIA Receiver End of Cell 43.2.2 Transmit Cell Transfer Operation Assertion of the TxClav signal generates a request for a cell to transmit. The MPC850SR’s UTOPIA interface implements the cell level handshake, and the PHY must be able to receive a whole cell upon assertion of the TxEnb signal.
Page 1000: Utopia Multi-Phy Operations
The MPC850SR supports a multi-PHY interface through the use of PHY addressing signals. The following are guidelines for Multi-PHY operation: • Up to 4 PHYS may be supported. • Supports using additional PHY addressing signals - PHREQ and PHSEL. MPC850 Family User’s Manual...

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Freescale Semiconductor MPC850 User Manual

Overview

Section 2

Chapter 16 System Configuration

Section 3

Appendix C

Appendix D

Appendix E

Chapter 1 Powerpc Microprocessor Module

Chapter 15 Memory Controller

Chapter 2 Memory Map

Chapter 3

Chapter 4 Powerpc User-Level Register Bit Assignments

Chapter 5

Chapter 6 Exception Ordering

Chapter 7

Chapter 8

Chapter 9

Chapter 10

Chapter 11

Chapter 12

Chapter 13

Chapter 14

Chapter 19

Chapter 20

Chapter 28 SCC Transparent Mode

Chapter 21

Chapter 22 Scc Uart Mode

Chapter 23

Chapter 24

Chapter 25

Chapter 26

Chapter 27 Scc Ethernet Mode

Chapter 35

Chapter 34 Parallel I/O Ports

Chapter 29

Chapter 30 SMC Features

Chapter 18

Chapter 31 SPI Clocking and Signal Functions

Chapter 45

Chapter 32

Chapter 33

Chapter 38 ATM Parameter RAM

Chapter 36

Chapter 39 ATM Controller

Chapter 40 ATM Pace Control

Chapter 37

Chapter 41 ATM Exceptions

Chapter 42 General ATM Registers

Chapter 43

Chapter 44

Chapter 17 Communications Processor

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Summary of Contents for Freescale Semiconductor MPC850