Freescale Semiconductor MPC5200B User Manual page 644

$__35,$__B5
$__38,$__B8
$__39,$__B9
$__3C,$__BC
$__3D,$__BD
$__40 -$__5F,
$__C0 -$__DF
$__60 -$__7F,
$__E0 -$__FF
a
Refer to detailed register description for write access restrictions on per bit basis.
b
Reserved bits and unused bits within the TX- & RX-Buffers (CANTXFG, CANRXFG) will be read
as "X", because of RAM based implementation.
19.5.2 Register Descriptions
This section describes in detail all the registers and register bits in the MSCAN module. Each description includes a standard register diagram
with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order. All bits of all registers in
this module are completely synchronous to internal clocks during a register read.
The registers are located at an offset from MBAR of 0x0900 (MSCAN1) and 0x0980 (MSCAN2) . Register addresses are relative to this
offset.
19.5.3 MSCAN Control Register 0 (CANCTL0)—MBAR + 0x0900 / 0x980
R
W
RESET:
The MSCAN Control Register 0, CANCTL0, provides for various control of the MSCAN Module.
NOTE: The MSCAN Control Register 0, except the WUPE, INITRQ and SLPRQ bits, is held in the reset state when the Initialization Mode
is active (INITRQ = 1 and INITAK = 1). This register is writable again as soon as the Initialization Mode is exited (INITRQ = 0 and INITAK
= 0).
Read: Anytime
Write: Anytime when out of Initialization; exceptions are bits RXACT and SYNCH which are read-only and bit RXFRM which is set by the
module. A write of '1' to the RXFRM register clears the flag and a write of '0' is ignored.
Freescale Semiconductor
Table 19-2. Module Memory Map (continued)
MSCAN Identifier Acceptance Register 7 (CANIDAR7)
MSCAN Identifier Mask Register 4 (CANIDMR4)
MSCAN Identifier Mask Register 5 (CANIDMR5)
MSCAN Identifier 6 Mask Register 6 (CANIDMR6)
MSCAN Identifier Mask Register 7 (CANIDMR7)
Foreground Receive Buffer (CANRXFG)
Foreground Transmit Buffer (CANTXFG)
Table 19-3. MSCAN Control Register 0
msb 0 1 2
0 0 0
MPC5200B Users Guide, Rev. 1
Memory Map / Register Definition
3 4 5 6
0 0 0 0
R/W
R/W
R/W
R/W
R/W
b
R
2
R /W
7 lsb
1
19-5