Psc Operation Modes - Freescale Semiconductor MPC5200B User Manual

Bit Name
3 SHDIR
4:7 SIM[3:0]
8 GenClk
9 I2S
10 ClkPol
11 SyncPol
12 CellSlave
Freescale Semiconductor
PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00
Codec—Shift Direction.
0 = msb first
1 = lsb first
other Modes—Reserved
PSC operation mode.
CAUTION: When the operating mode change occurs, all Rx/Tx and error statuses are reset.
Rx and Tx are disabled.
0000 = UART mode, DCD input ignored
1000 = UART mode, DCD input is effective
x001 = Codec mode, 8-bit data
x010 = Codec mode, 16-bit data
x011 = AC97 mode
0100 = SIR model, DCD input ignored
1100 = SIR mode, DCD input is effective
x101 = MIR mode
x110 = FIR mode
0111 = Codec mode, 24-bit data
1111 = Codec mode, 32-bit data
Codec—Generate Bit Clock and FrameSync, not used to enable the SPI master mode, use
the MSTR bit of the this register
0 = use bit clock and FrameSync provided by external device
1 = use bit clock and FrameSync generated internally from Mclk
MIR / FIR—Generate Bit Clock and FrameSync
0 = use for clock generation the external Clk from Pad IR_USB_CLK
1 = use for clock generation the internal Mclk
other Modes—Reserved
Codec—I2S mode
0 = no I2S mode supported
1 = PSC works in I2S mode
other Modes—Reserved
Codec—Bit Clock Polarity
0 = data in is sampled on the falling edge of the BitClk and data out is shifted on the rising
edge
1 = data in is sampled on the rising edge of the BitClk and data out is shifted on the falling
edge
other Modes—Reserved
Codec—FrameSync Polarity
0 = FrameSync is low true
1 = FrameSync is high true
Codec I2S—FrameSync Polarity
0 = Frame starts if LRCK is low
1 = Frame starts if LRCK is high
other Modes—Reserved
Codec—Cell Phone Slave
0 = PSC is not a slave to PSC1
1 = PSC uses Bit Clock from PSC1 master as its Mclk
MPC5200B Users Guide, Rev. 1
Description
15-31