Freescale Semiconductor MPC5200B User Manual page 16

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Number
17.1 Overview .................................................................................................................................................................17-1
17.1.1 Features .............................................................................................................................................................17-1
17.1.2 Modes of Operation ..........................................................................................................................................17-1
17.2 SPI Signal Description ............................................................................................................................................17-2
17.2.1 Master In/Slave Out (MISO) ...........................................................................................................................17-2
17.2.2 Master Out/Slave In (MOSI) ...........................................................................................................................17-2
17.2.3 Serial Clock (SCK) ...........................................................................................................................................17-3
17.2.4 Slave-Select (SS) ..............................................................................................................................................17-3
17.3 SPI Registers-MBAR + 0x0F00 ...........................................................................................................................17-3
17.3.1 SPI Control Register 1-MBAR + 0x0F00 ......................................................................................................17-3
17.3.2 SPI Control Register 2-MBAR + 0x0F01 ......................................................................................................17-4
17.3.3 SPI Baud Rate Register-MBAR + 0x0F04 ....................................................................................................17-5
17.3.4 SPI Status Register -MBAR + 0x0F05 ..........................................................................................................17-6
17.3.5 SPI Data Register-MBAR + 0x0F09 ..............................................................................................................17-7
17.3.6 SPI Port Data Register-MBAR + 0x0F0D .....................................................................................................17-7
17.3.7 SPI Data Direction Register-MBAR + 0x0F10 ..............................................................................................17-7
18.1 Overview .................................................................................................................................................................18-1
18.1.1 Features .............................................................................................................................................................18-1
2
18.2 I C Controller ..........................................................................................................................................................18-2
18.2.1 START Signal ...................................................................................................................................................18-2
18.2.2 STOP Signal ......................................................................................................................................................18-2
18.2.2.1
18.2.2.2
18.2.2.3
18.2.2.4
18.2.2.5
2
18.3 I C Interface Registers ............................................................................................................................................18-5
2
18.3.1 I C Address Register (MADR)-MBAR + 0x3D00 ........................................................................................18-5
2
18.3.2 I C Frequency Divider Register (MFDR)-MBAR + 0x3D04 ........................................................................18-6
2
18.3.3 I C Control Register (MCR)-MBAR + 0x3D08 ............................................................................................18-7
2
18.3.4 I C Status Register (MSR)-MBAR + 0x3D0C ..............................................................................................18-8
2
18.3.5 I C Data I/O Register (MDR)-MBAR+ x3D10 ..........................................................................................18-10
2
18.3.6 I C Interrupt Control Register-MBAR + 0x3D20 ........................................................................................18-10
18.4 Initialization Sequence ..........................................................................................................................................18-11
18.5 Transfer Initiation and Interrupt ............................................................................................................................18-11
18.5.1 Post-Transfer Software Response ...................................................................................................................18-12
18.5.2 Slave Mode .....................................................................................................................................................18-12
19.1 Overview .................................................................................................................................................................19-1
19.2 Features ...................................................................................................................................................................19-2
19.3 External Signals .......................................................................................................................................................19-2
19.3.1 RXCAN - CAN Receiver Input Pin ...............................................................................................................19-2
19.3.2 TXCAN - CAN Transmitter Output Pin ........................................................................................................19-2
19.4 CAN System ............................................................................................................................................................19-2
19.5 Memory Map / Register Definition .........................................................................................................................19-3
19.5.1 Module Memory Map .......................................................................................................................................19-3
19.5.2 Register Descriptions ........................................................................................................................................19-5
19.5.3 MSCAN Control Register 0 (CANCTL0)-MBAR + 0x0900 ........................................................................19-5
Freescale Semiconductor
Chapter 17 Serial Peripheral Interface (SPI)
Chapter 18 Inter-Integrated Circuit (I
Slave Address Transmission .......................................................................................................................18-3
Data Transfer ..............................................................................................................................................18-3
Acknowledge ..............................................................................................................................................18-3
Repeated Start .............................................................................................................................................18-4
Clock Synchronization and Arbitration ......................................................................................................18-4
Chapter 19 Motorola Scalable CAN (MSCAN)
MPC5200B Users Guide, Rev. 1
Table of Contents
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Number
TOC-15