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ATA Register Interface
Bits
Name
0:7
pio_t0
8:15
pio_t2_8
16:23
pio_t2_16
24:31
—
11.3.1.4
ATA PIO Timing 2 Register—MBAR + 0x3A0C
msb 0
1
R
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Bits
Name
0:7
pio_t4
8:15
pio_t1
16:23
pio_ta
24:31
—
11.3.1.5
ATA Multiword DMA Timing 1 Register—MBAR + 0x3A10
msb 0
1
R
W
RESET:
0
0
16
17
R
W
RESET:
0
0
11-4
PIO cycle time count value is based on system clock operating frequency.
PIO read/write pulse width for 8-bit transfers. Count value is based on system clock
operating frequency.
PIO read/write pulse width for 16-bit transfers. Count value is based on system clock
operating frequency.
Reserved
Table 11-4. ATA PIO Timing 2 Register
2
3
4
5
6
pio_t4
0
0
0
0
0
18
19
20
21
22
pio_ta
0
0
0
0
0
PIO write (DIOW) data hold time. Count value is based on system clock operating frequency.
Address valid to DIOR/DIOW setup. Count value is based on system clock operating
frequency.
IORDY setup time. Count value is based on system clock operating frequency.
Reserved
Table 11-5. ATA Multiword DMA Timing 1 Register
2
3
4
5
6
dma_t0
0
0
0
0
0
18
19
20
21
22
dma_tk
0
0
0
0
0
MPC5200B Users Guide, Rev. 1
Description
7
8
9
10
11
0
0
0
0
23
24
25
26
27
0
0
0
0
Description
7
8
9
10
11
0
0
0
0
23
24
25
26
27
0
0
0
0
12
13
14
15
pio_t1
0
0
0
0
0
28
29
30
31 lsb
Reserved
0
0
0
0
0
12
13
14
15
dma_td
0
0
0
0
0
28
29
30
31 lsb
dma_tm
0
0
0
0
0
Freescale Semiconductor
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