Freescale Semiconductor MPC5200B User Manual page 591

XLB Arbiter Registers—MBAR + 0x1F00
msb 0 1
R PLDIS
W
RESET: 1 0
16 17
R SE USE_
WWF
W
RESET: 0 0
Bit Name
0 PLDIS
1:14 —
15 BSDIS
16 SE
17 USE_WWF
18 TBEN
19 —
20 WS
21:23 SP[2:0]
24 —
16-4
Table 16-1. Arbiter Configuration Register
2 3 4 5 6
0 0 0 0 0
18 19 20 21 22
TBEN Rsvd WS SP
0 0 0 0 0
Pipeline Disable. This bit is used to enable or disable transaction pipelining on the XLB. See
note below.
0 = Enable pipelining
1 = Disable pipelining
Reserved
BestComm Snooping Disable.
0 = BestComm XLB addresss snooping enabled.
1 = BestComm XLB addresss snooping disabled.
Snoop Enable. This sets the address snooping enablement on the XLB.
0 = Disable address snooping. Internally on the XLB, the gbl_b signal is gated (always
negated). This overrides any setting of the
+ 0x1F70.
1 = Allow address snooping. Internally on the XLB, the gbl_b signal is not gated, and
assertions of this signal during address tenures will be recognized.
Force write-with-flush transfer type (TT) for PCI, BestComm, and USB interfaces to XLB.
0 = Write-with-kill operation is allowed on burst transactions.
1 = Always use write-with-flush on burst transactions.
Timebase Enable. This bit is used as a "count enable" control input for the timebase counter
in the 603e core.
0 = Timebase should stop clocking.
1 = Timebase should continue clocking.
Reserved
Minimum Wait State. This bit sets the minimum number of wait states for slaves to respond
with AACK assertion on the XLB.
0 = 0 minimum wait state.
1 = 1 minimum wait state.
Select Parked Master. These bits set the master that is used in Park on Programmed
Master mode (000 = master 0, 001 = master 1, ..., 111 = master 7).
Reserved
MPC5200B Users Guide, Rev. 1
7 8 9 10 11
Rsvd
0 0 0 0 0
23 24 25 26 27
Rsvd PM Rsvd
0 0 0 0 0
Description
Arbiter Snoop Window Register (RW)—MBAR
12 13 14 15
BSDIS
0 0 0 0
28 29 30 31 lsb
BA DT AT Rsvd
0 1 1 0
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