Freescale Semiconductor MPC5200B User Manual page 168

Bits Name
8:11 Per18_pri
12:15 Per19_pri
16:19 Per20_pri
20:23 Per21_pri
24 :27 Per22_pri
28 :31 Per23_pri
7.2.4.5 ICTL External Enable and External Types Register —MBAR + 0x0510
Table 7-8. ICTL External Enable and External Types Register
msb 0 1
R Reserved
W
RESET: 0 0
16 17
R Reserved
W
RESET: 0 0
Bits Name
0:3 —
— ECLR[x]
4 ECLR0
5 ECLR1
6 ECLR2
7 ECLR3
8:9 Etype0
10:11 Etype1
12:13 Etype2
14:15 Etype3
16:18 —
19 MEE
Freescale Semiconductor
Peripheral 18 = CAN2
Reserved
Reserved
Peripheral 21 = XLB Arbiter
Peripheral 22 = BDLC
Peripheral 23 = BestComm LocalPlus
2 3 4 5 6
ECLR(4)
0 0 0 0 0
18 19 20 21 22
MEE EENA(4)
0 0 0 0 0
Reserved
These bits clear external IRQ interrupt indications. When an IRQ input is configured as an
edge-sensitive input, the Interrupt Controller must be notified that the specific interrupt has
been serviced. Software must write 1 to the appropriate bit position to clear the interrupt
indication. ECLR bits are always read as 0 (i.e., they do not contain status).
IRQ[0], write 1 to clear
IRQ[1], write 1 to clear
IRQ[2], write 1 to clear
IRQ[3], write 1 to clear
These bits control how the Interrupt Controller interprets the IRQ[0] input pin.
00 = Input is level sensitive and active hi
01 = Input is edge sensitive, rising edge active"
10 = Input is edge sensitive, falling edge active"
11 = Input is level sensitive, and active low"
Same as above, but for the IRQ[1] input pin.
Same as above, but for the IRQ[2] input pin.
Same as above, but for the IRQ[3] input pin.
Reserved—unused bits, writing has no effect, always read as 0.
Master External Enable—clearing this bit masks all IRQ input transitions (including status
indications).
MPC5200B Users Guide, Rev. 1
Description
7 8 9 10 11
Etype0 Etype1
0 0 0 0
23 24 25 26 27
Reserved
0 0 0 0
Description
Interrupt Controller
12 13 14 15
Etype2 Etype3
0 0 0 0 0
28 29 30 31 lsb
CEb
0 0 0 0 0
7-9