Gpio Pin Multiplexing; Gpio/Generic Mux Cell - Freescale Semiconductor MPC5200B User Manual

7.3.1

GPIO Pin Multiplexing

Figure 7-3 shows the GPIO/Generic MUX cell.
Alternate Func 1
IN
Enabled
Alternate Func 2
IN
Enabled
TIMER
IN
Enabled
GPIO/d/W
ODconfig
IN
Enabled
Awake
Note:
1. Open-Drain Emulation is supported on the GPIO function.
2. Pin MUX Logic is controlled by the Port Configuration Register and supersedes any individual
GPIO register programming.
Freescale Semiconductor
Pin MUX Logic
OUT
BC
OUT
BC
OUT
BC
OUT
BC
Interrupt for WakeUp supported GPIO pins only
Figure 7-3. GPIO/Generic MUX Cell
MPC5200B Users Guide, Rev. 1
Priority
Output Enable
Logic
General Purpose I/O (GPIO)
I/O Cell
Multi-
Function
I/O
7-25