Mscan Receive Error Counter Register (Canrxerr)—Mbar + 0X091C; Mscan Transmit Error Counter Register (Cantxerr)—Mbar + 0X091D - Freescale Semiconductor MPC5200B User Manual

19.5.15 MSCAN Receive Error Counter Register (CANRXERR)-MBAR + 0x091C / 0x099C
R
W
RESET:
READ: Only when in Sleep Mode (SLPRQ = 1 and SLPAK = 1) or Initialization Mode (INITRQ = 1 and INITAK =1).
WRITE: Unimplemented
Bit Name
0:7 RxERR[7:0]
Reading this register when in any other mode other than sleep or Initialization may return an incorrect
value.
Writing to these registers when in special modes can alter the MSCAN functionality.
19.5.16 MSCAN Transmit Error Counter Register (CANTXERR)-MBAR + 0x091D/0x099D
R
W
RESET:
Note: This register reflects the status of the MSCAN transmit error counter.
READ: Only when in Sleep Mode (SLPRQ = 1 and SLPAK = 1) or Initialization Mode (INITRQ = 1 and INITAK =1).
WRITE: Unimplemented
Bit Name
0:7 TxERR[7:0]
Reading this register when in any other mode other than sleep or Initialization may return an incorrect
value.
Writing to these registers when in special modes can alter the MSCAN functionality.
Freescale Semiconductor
Table 19-20. MSCAN Receive Error Counter Register
msb 0 1 2
0 0 0
This register reflects the status of the MSCAN receive error counter.
Table 19-21. MSCAN Transmit Error Counter Register
msb 0 1 2
0 0 0
This register reflects the status of the MSCAN transmit error counter.
MPC5200B Users Guide, Rev. 1
3 4 5
RxERR[7:0]
0 0 0
Description
NOTE
NOTE
3 4 5
TxERR[7:0]
0 0 0
Description
NOTE
NOTE
Memory Map / Register Definition
6 7 lsb
0 0
6 7 lsb
0 0
19-17