Freescale Semiconductor MPC5200B User Manual page 330

16 17
R Reserved
W
RESET 0 0
Bits Name
0:19 Reserved
20:31 Alarm
Freescale Semiconductor
18 19 20 21 22
Alarm
0 0 0 0 0
Unused. Software should write zero to these bits.
User writes these bits to set low level "watermark", which is the point where FIFO asserts
request for Multi-Channel DMA controller data filling. Value is in Bytes. For example, with
Alarm = 32, alarm condition occurs when FIFO contains less than 32Bytes. Once asserted,
alarm does not negate until high level mark is reached, as specified by FIFO control register
granularity (GR) bits.
Note: An Alarm setting less than the value of Max_Beats x 4 should be avoided. The
transmit operation waits for the data to be stored in the FIFO before transmission onto the
PCI bus. (e.g. A Max_setting of 0 represents eight beats (32-bits each) per transaction. The
value of Alarm is in bytes. Ex: the value programmed to the Alarm register should be at least
0x20 (32 bytes) for the Multi-Channel DMA to continue to write enough data to complete at
least one PCI burst.)
Note: TX PCI FIFO is 512 bytes deep.
MPC5200B Users Guide, Rev. 1
23 24 25 26 27
0 0 0 0
Description
Registers
28 29 30 31 lsb
Alarm
0 0 0 0 0
10-33