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15.2.4.5 PCI Error Address Capture Register (PCI_EACR)
PCI_EACR
Bit
31
30
29
Type
Reset
0
0
0
Bit
15
14
13
Type
Reset
0
0
0
PCI_EACR stores the low portion of the address associated with the first PCI error captured.
Table 15-28 shows the PCI_EACR bit field.
Bits
PCI_EA
PCI Error Address
31–0
Contains the low portion of the address associated with the first detected error.
15.2.4.6 PCI Error Extended Address Capture Register (PCI_EEACR)
PCI_EEACR
Bit
31
30
29
Type
Reset
0
0
0
Bit
15
14
13
Type
Reset
0
0
0
PCI_EEACR stores the high portion of the address associated with the first PCI error captured.
Table 15-29 shows the PCI_EEACR bit field.
Bits
PCI_EEA
PCI Error Extended Address
31–0
Contains the high portion of the address associated with the first detected error.
Freescale Semiconductor
PCI Error Address Capture Register
28
27
26
25
0
0
0
0
12
11
10
9
0
0
0
0
Table 15-28. PCI_EACR Field Descriptions
PCI Error Extended Address Capture Register
28
27
26
25
0
0
0
0
12
11
10
9
0
0
0
0
Table 15-29. PCI_EEACR Field Descriptions
MSC8144E Reference Manual, Rev. 3
24
23
22
21
PCI_EA
R/W
0
0
0
0
8
7
6
5
PCI_EA
R/W
0
0
0
0
Description
24
23
22
21
PCI_EEA
R/W
0
0
0
0
8
7
6
5
PCI_EEA
R/W
0
0
0
0
Description
Programming Model
Offset 0x010
20
19
18
17
0
0
0
0
4
3
2
1
0
0
0
0
Offset 0x014
20
19
18
17
0
0
0
0
4
3
2
1
0
0
0
0
16
0
0
0
16
0
0
0
15-39
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