Freescale Semiconductor MPC5200B User Manual page 587

PSC FIFO System
TxD
Transmitter
Enabled
SR [TxRDY]
internal
module
select
MR1n[PM] = 11
MR1n[PT] = 1
RxD
Receiver
Enabled
SR[RxRDY]
internal
module
select
MR1n[PM] = 11
MR1n[PM] = 11
A character sent from the master station consists of:
• a start bit
• a programmed number of data bits
• an address/data (A/D) bit flag
— A/D=1 indicates an address character
— A/D=0 indicates a data character
• a programmed number of stop bits
A/D polarity is selected through MR1[PT].
bits into the Tx buffer.
In multidrop mode, the receiver continuously monitors the received data stream, regardless of whether it is enabled or disabled.
• If the receiver is disabled, it sets the RxRDY bit and loads the character into the receiver holding register FIFO stack, provided the
received A/D bit is 1 (address tag). If the received A/D bit is 0 (data tag), the character is discarded.
• If the receiver is enabled, all received characters are transferred to the CPU through the receiver holding register stack during read
operations.
In either case, data bits are loaded into the data portion of the stack while the A/D bit is loaded into the status portion of the stack normally
used for a parity error (SR[PE]).
Framing error, overrun error, and break detection operate normally. The A/D bit takes the place of the parity bit. Parity is neither calculated
nor checked. Messages in this mode may still contain error detection and correction information. One way to provide error detection if 8-bit
characters are not required, is to use software to calculate parity and append it to the 5-, 6-, or 7-bit character.
15-76
Master Station
A/D A/D
ADD1 1 C0
ADD 1 C0
MR1n[PT] = 0
Peripheral Station
A/D A/D A/D
0 ADD1 1 C0
ADD 1
Figure 15-26. Timing Diagram—Multidrop Mode
MR1 should be programmed before enabling the transmitter and loading the corresponding data
MPC5200B Users Guide, Rev. 1
ADD2
ADD 2
MR1n[PT] = 2
ADD2
Status Data
(C0)
A/D
1
A/D A/D
1 0
Status Data
(ADD 2)
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