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ATA Register Interface
11.3.3.4
ATA Drive Features Register—MBAR + 0x3A64
msb 0
1
R
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Bits
Name
0:7
Data
8:31
—
11.3.3.5
ATA Drive Error Register—MBAR + 0x3A64
msb 0
1
R
W
RESET:
0
0
16
17
R
W
RESET:
0
0
Bits
Name
0:4
Data
5
ABRT
0:7
Data
8:31
—
11-14
Table 11-22. ATA Drive Features Register
2
3
4
5
6
Data
0
0
0
0
0
18
19
20
21
22
0
0
0
0
0
Register content is command dependent. Contents become command parameters when the
ATA drive command register is written.
Reserved
Table 11-23. ATA Drive Error Register
2
3
4
5
Data
ABRT
0
0
0
0
18
19
20
21
22
0
0
0
0
0
Register content is command dependent. Contents become command parameters when the
ATA drive command register is written.
Register content is valid when BSY and DRQ bits are set to 0 and ERR bit is set to 1 in the
ATA drive status register. Register content is not valid when drive is in sleep mode.
Bit is set to 1 to indicate requested command has been aborted, because command code or
a command parameter is invalid or some other error occurred.
Register content is command dependent. Contents become command parameters when the
ATA drive command register is written.
Register content is valid when BSY and DRQ bits are set to 0 and ERR bit is set to 1 in the
ATA drive status register. Register content is not valid when drive is in sleep mode.
Reserved
MPC5200B Users Guide, Rev. 1
7
8
9
10
0
0
0
0
23
24
25
26
Reserved
0
0
0
0
Description
6
7
8
9
10
Data
0
0
0
0
0
23
24
25
26
Reserved
0
0
0
0
Description
11
12
13
14
15
Reserved
0
0
0
0
27
28
29
30
31 lsb
0
0
0
0
11
12
13
14
Reserved
0
0
0
0
27
28
29
30
31 lsb
0
0
0
0
Freescale Semiconductor
0
0
15
0
0
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