Freescale Semiconductor MPC5200B User Manual page 530

Bit Name
6 IEC1
7 IEC0
15.2.10 Interrupt Status Register (0x14)
The read-only ISR register provides status for all potential interrupt sources. Register contents is masked by the IMR.
• If an ISR flag sets and the corresponding
• If the corresponding IMR
Table 15-26. Interrupt Status Register (0x14) for UART / SIR Mode
msb 0 1
R IPC Reserved
W
RESET: 0 0
msb 0 1
R IPC Reserved
W
RESET: 0 0
Bit Name
0 IPC
1 :2 —
3 ORERR
Freescale Semiconductor
PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00
Interrupt enable control for D_DCD.
0 = D_DCD has no effect on the IPC in the ISR.
1 = When the D_DCD becomes high, IPC bit in the
is set).
Interrupt enable control for D_CTS.
0 = D_CTS has no effect on the IPC in the ISR.
1 = When the D_CTS becomes high, IPC bit in the
is set).
After enable the PSC the D_CTS bit can be set, therefore it's important to clear the D_CTS bit
before enable this interrupt.
IMR bit is also set, the internal interrupt output is asserted.
bit is cleared, the ISR bit state has no effect on the interrupt output.
2 3 4 5 6
DB
0 0 0 0 0
Table 15-27. Interrupt Status Register (0x14) other Modes
2 3 4 5 6
0 0 0 0 0
Input port change interrupt.
0 = No IPC event was occurred.
1 = An IPC event was occurred.
Reserved
Overrun Error
This bit is identical to the ORERR bit in the
error status command in the
MPC5200B Users Guide, Rev. 1
Description
ISR
ISR
ISR
—
7 8 9 10
Error
0 0 0 0
7 8 9 10
Error Reserved
0 0 0 0
Description
SR register. To clear this interrupt use the reset
CR register.
sets (causing an interrupt if mask
sets (causing an interrupt if mask
11 12 13 14 15 lsb
Reserved
0 0 0 0
11 12 13 14 15 lsb
0 0 0 0
0
0
15-19