Freescale Semiconductor MPC5200B User Manual page 153

CDM Registers
5.5.9 CDM Soft Reset Register—MBAR + 0x0220
This register contains 2 reset control bits.
msb 0 1
R
W
RESET: 0 0
16 17
R
W
RESET: 0 0
Bit Name
0–6 —
7 cdm_soft_reset
8–14 —
15 cdm_no_ckstp_reset CDM No reset on checkstop.
16–31 —
5.5.10 CDM System PLL Status Register—MBAR + 0x0224
This register contains control and status bits of the CDM PLL lock detect module.
msb 0 1
R
W
RESET: 0 0
16 17
R
W
RESET: 0 0
5-20
Table 5-16. CDM Soft Reset Register
2 3 4 5
Reserved
Write 0
0 0 0 0
18 19 20 21 22
0 0 0 0
Reserved for future use. Write 0.
CDM Soft Reset bit.
bit=0:requests CDM soft reset.
bit=1:CDM soft reset request inactive.
Reserved for future use. Write 0.
bit=0:Checkstop assertion causes HRESET.
bit=1:Checkstop assertion does not cause HRESET.
Reserved for future use. Write 0.
Table 5-17. CDM System PLL Status Register
2 3 4 5
Reserved
Write 0
0 0 0 0
18 19 20 21 22
Reserved
Write 0
0 0 0 0
MPC5200B Users Guide, Rev. 1
6 7 8 9 10
0 1 0 0 0
23 24 25 26
Reserved
Write 0
0 0 0 0 0
Description
6 7 8 9 10
0 — 0 0 0
23 24 25 26
0 1 0 0 0
11 12 13 14
Reserved
Write 0
0 0 0 0
27 28 29 30
0 0 0 0
11 12 13 14
Reserved
Write 0
0 0 0 0
27 28 29 30
Reserved
Write 0
0 0 0 0
Freescale Semiconductor
15
0
31 lsb
0
15
0
31 lsb
0