Block Diagram—Sdram Subsystem Example - Freescale Semiconductor MPC5200B User Manual

Features
Figure 8-1 shows an example memory configuration of 1 space (CS) of 4 devices of 128Mbit (4M x 4 banks x 8bit) DDR SDRAM, for a total
memory size of 64MB.
Glue
A_CS
D_CS
R/W
DM[0:7]
REG_CS
REGD_CS
processor bus
Note: For 16-Bit External Data Width,
mem_ps = 1, only DQ[31:16] should
be connected to the external memories.
Both chip selects contribute together to access the whole memory. Each CS base address and size are programmed independently. Each CS
base address must be size-aligned.
The MPC5200B does not support DIMM memory modules, however it can support a DIMM-compatible EEPROM using an on-chip I
interface (with appropriate configuration of pin functions).
8-14
SDRAM
Memory Controller
A_CS
DQ[31:0]
D_CS
BA[1:0]
CLK
R/W
CLK
DM_I[0:7]
CKE
REG_CS
REGD_CS
CS[0]
DI[0:63]
CS[1]
ADDR[4:29]
RAS
AACK
CAS
ARTRY
DQS[3:0]
TBST
DM[3:0]
DO[0:63]
MA[11:0]
TA
WE
RESET
CLK
Figure 8-1. Block Diagram—SDRAM Subsystem Example
MPC5200B Users Guide, Rev. 1
7:0
DQ[7:0]
BA[1:0]
CLK
CLK
CKE
CS
RAS
CAS
0
DQS
0
DM
A[11:0]
WE
A[11:0]
DQ[31:0]
23:16
DQ[7:0]
BA[1:0]
CLK
CLK
CKE
CS
RAS
CAS
2
DQS
2
DM
A[11:0]
WE
15:8
DQ[7:0]
BA[1:0]
CLK
CLK
CKE
CS
RAS
CAS
1
DQS
1
DM
A[11:0]
WE
31:24
DQ[7:0]
BA[1:0]
CLK
CLK
CKE
CS
RAS
CAS
3
DQS
3
DM
A[11:0]
WE
2
C chip
Freescale Semiconductor