Freescale Semiconductor MPC5200B User Manual page 534

15.2.13 Counter Timer Lower Register (0x1C)
This write-only register hold the lower bytes of the preload value used by the timer to provide a given Baud rate. Reading from this register
shows the current value of the Baud rate generation counter.
Table 15-31. Counter Timer Lower Register (0x1C) for all Modes
msb 0
R
W
RESET: 0
Bit Name
0:7 CTLR
DTL — Length of Delay after Transfer
When the PSC is in SPI mode (SICR[SPI] = 1), the Counter Timer is used to determine the length of time that the PSC delays after each
serial transfer, i. E. the length of time that SS stays high/inactive between consecutive transfers. This is a feature that exists in a QSPI.
Delay after transfer can be used to ensure that the deselect time requirement (for peripherals having such a requirement) is met. Some
peripherals must be deselected for a minimum period of time between consecutive serial transfers. A delay after transfer can be inserted
between consecutive transfers to a given peripheral to ensure that its minimum deselect time requirement is met or to allow serial A/D
converters to complete conversion before the next transfer is made.
15.2.14 Codec Clock Register (0x20)—CCR
This register defines the divider for the FrameSync and BitClk generation for Codec mode. This register value has only effect, if the GenClk
bit in the PSC Control Register
Table 15-32. Codec Clock Register (0x20)—CCR for Codec Mode
msb 1
0
RESET: 0 0
Freescale Semiconductor
PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00
1 2
0 0
UART—Baud rate prescale value. The Baud rate is calculated as:
IPB clock frequency
Baud rate =
CT[0:15] x "prescaler"
The minimum CT value is 1; 0 denotes counter stop.
The prescaler was defined in the
SIR—Baud rate prescale value. The Baud rate is calculated as:
IPB clock frequency
Baud rate =
CT[0:15] x 32
The minimum CT value is 1; 0 denotes counter stop.
SPI—Delay After Transfer (DTL)
CT[0:15] + 2
DTL =
]
IPB clock frequency
where:
CT[0:15] = {CTUR[0:7], CTLR[0:7]}
Other—Reserved
SICR was set to one. In UART, SIR and AC97 mode this register is reserved.
2 3 4 5 6
0 0 0 0 0
MPC5200B Users Guide, Rev. 1
CTLR
—
3 4 5
Reserved
CTLR[0:7]
0 0 0
Description
where:
CT[0:15] = {CTUR[0:7], CTLR[0:7]}
CSR register.
where:
CT[0:15] = {CTUR[0:7], CTLR[0:7]}
3
+
Mclk frequency
7 8 9 10
0 0 0 0
6 7 lsb
0 0
11 12 13 14 15 lsb
0 0 0 0 1
15-23