Table of Contents
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Chapter 11
ATA Controller
11.1
Overview
The following sections are contained in this document:
•
Section 11.2, BestComm Key Features
—
Section 11.3, ATA Register
—
Section 11.3.1, ATA Host Registers—MBAR + 0x3A00
—
Section 11.3.2, ATA FIFO Registers—MBAR + 0x3A00
—
Section 11.3.3, ATA Drive Registers—MBAR + 0x3A00
•
Section 11.4, ATA Host Controller Operation
•
Section 11.5, Signals and Connections
•
Section 11.6, ATA Interface Description
•
Section 11.7, ATA Bus Background
•
Section 11.8, ATA RESET/Power-Up
•
Section 11.9, ATA I/O Cable Specifications
The Advanced Technology Attachment (ATA) Controller provides full functional compatibility with ATA-4 documentation, supporting
Ultra-33. For more ATA Standards information, refer to "American National Standard for Information Technology—AT Attachment with
Packet Interface Extension (ATA/ATAPI-4)".
A dedicated MPC5200B pin for ATA reset is not provided. An appropriate signal on the board should be routed to the reset input on the ATA
connector. If ATA reset is tied to
period of time to satisfy ATA reset. An MPC5200B GPIO may be used to drive ATA reset independently if special software control is needed.
Figure 11-1
shows the ATA Controller Interface.
(higher priority)
BestComm
IPBI
11.2
BestComm Key Features
11.2.1
BestComm Read
1.
microprocessor sets up descriptors in BestComm RAM and initiates a transfer.
2.
BestComm hits on an ATA command FIFO space and writes a command (ATA drive register address, transfer size) into FIFO.
3.
ATA Controller reads data from the drive and puts data in FIFO.
Freescale Semiconductor
Interface, includes:
HRESET
SRESET
or
on MPC5200B pins, they are asserted and internally held low for an appropriate
IP bus
ARB
Figure 11-1. ATA Controller Interface
MPC5200B Users Guide, Rev. 1
Rx/Tx FIFO
Interface
IPBI
Overview
PCI Handshake
ATA Host
Controller
Ultra DMA
Channel
Multiword
DMA
Channel
Program
Local Bus
Registers
(Host/Driver)
PIO
Channel
11-1
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